MC68EC030FE40C Freescale Semiconductor, MC68EC030FE40C Datasheet - Page 17

• Manufacturer Part Number: MC68EC030FE40C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC030FE40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

ACCESS CONTROL
M O T O R O L A
Two access control registers are provided on the MC68EC030 to control cachability of accesses for two
independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is
specified in the corresponding ACx register with a base address, a base mask, function code, function
code mask, and read/write mask. A typical use for an access control register is to designate a block of
memory containing I/O devices as non-cachable.
The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The
interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of
these extensions are the addition of specialized data operands for the existing data types or, for the case
of floating point, the inclusion of new data types and operations
MC68881/MC68882 floating-point coprocessors.
Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.
ASYNCHRONOUS
BUS CONTROL
TRANSFER
FUNCTION
ADDRESS
CONTROL
CODES
CACHE
DATA
BUS
SIZE
BUS
COPROCESSOR INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 8. Functional Signal Groups
SIGNAL DESCRIPTION
MC68EC030 TECHNICAL DATA
DSACK1
DSACK0
FC0–FC2
CIOUT
CBREQ
CBACK
D0–D31
DBEN
CIIN
A0–A31
R/W
RMC
SIZ1
OCS
ECS
SIZ0
AS
DS
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MC68EC030
REFILL
STATUS
V
GND (14)
IPEND
RESET
STERM
CC
IPL0
IPL1
IPL2
AVEC
BGACK
BERR
CDIS
HALT
CLK
BR
BG
(10)
INTERRUPT
CONTROL
BUS ARBITRATION
CONTROL
BUS EXCEPTION
CONTROL
SYNCHRONOUS
BUS CONTROL
EMULATOR
SUPPORT
implemented
by
the
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