MPC8349EVVAGDB Freescale Semiconductor, MPC8349EVVAGDB Datasheet - Page 69

IC MPU POWERQUICC II 672-TBGA

MPC8349EVVAGDB

Manufacturer Part Number
MPC8349EVVAGDB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet

Specifications of MPC8349EVVAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
672-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
672
Rohs Compliant
Yes
For Use With
MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8349EVVAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC8349EVVAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
Freescale Semiconductor
CFG_CLKIN_DIV
Table 60
at Reset
Low
Low
Low
Low
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
show the expected frequency values for the CSB frequency for select csb_clk to
1
Section 19, “Clocking,”
Table 58. System PLL Multiplication Factors (continued)
Table 59. CSB Frequency Options for Host Mode
SPMF
0010
0011
0100
0101
RCWL[SPMF]
0111
1000
1001
1010
1011
1100
1101
1110
1111
the LBIUCM, DDRCM, and SPMF parameters in the reset
Input Clock Ratio
csb_clk :
System PLL Multiplication Factor
2 : 1
3 : 1
4 : 1
5 : 1
2
× 10
× 11
× 12
× 13
× 14
× 15
× 7
× 8
× 9
16.67
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
100
125
25
33.33
100
133
166
2
Table 59
66.67
133
200
266
333
Clocking
69

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