GCIXP1200GB Intel, GCIXP1200GB Datasheet
GCIXP1200GB
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GCIXP1200GB Summary of contents
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... Intel IXP1200 Network Processor Specification Update March 2004 Notice: The IXP1200 Network Processor may contain design defects or errors known as errata. Char- acterized errata that may cause the IXP1200 Network Processor’s behavior to deviate from published specifications are documented in this specification update. ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Contents Preface ...............................................................................................................................................5 Summary Table of Changes...............................................................................................................7 Identification Information................................................................................................................11 Errata................................................................................................................................................12 Specification Changes......................................................................................................................34 Specification Clarifications..............................................................................................................36 Documentation Changes ..................................................................................................................38 Specification Update ® IXP1200 Network Processor Intel iii ...
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... IXP1200 Network Processor Intel iv Specification Update ...
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... IXP1200 Network Processor Family Development Tools User’s Guide IXP1200 Network Processor Family Hardware Reference IXP1200 Network Processor Family Microcode Software Reference IXP1200 Network Processor Family Microcode Example Software User’s Guide Specification Update ® Intel IXP1200 Network Processor Title Preface Part Number 278298 ...
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... Intel IXP1200 Network Processor Preface Nomenclature Errata are design defects or errors. These may cause the published (component, board, system) behavior to deviate from published specifications. Hardware and software designed to be used with any component, board, and system must consider all errata documented. ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the IXP1200 Network Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following ...
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... Intel IXP1200 Network Processor Summary Table of Changes Errata No Steppings Page Status NoFix NoFix X 12 Fixed X 13 Fixed X 13 Fixed NoFix X 14 Fixed X 14 Fixed 14 Fixed X 15 Fixed X 15 Fixed X 15 Fixed NoFix X 16 Fixed X 16 Fixed X 16 Fixed X 16 Fixed ...
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... Command Bus Arbitration Policy ® Intel IXP1200 Network Processor Summary Table of Changes ERRATA Bit Test & Set and Bit Test & Clear SRAM Operations from the StrongARM* Core Read-Lock CAM Operations from the StrongARM* Core to SRAM IXP1200 PCI_INT_LAT Register Bits [11:8] ...
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... Intel IXP1200 Network Processor Summary Table of Changes Specification Clarifications (Sheet No Documentation Changes No. Document Revision 10 Steppings Page SRAM Unlocks and Write Unlocks Maximum Number of Chain_Ref Instructions DMA Receive in Big Endian Mode Page None for this release of the document. SPECIFICATION CLARIFICATIONS DOCUMENTATION CHANGES ...
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... Identification Information Markings Product Name GCIXP1200EA GCIXP1200EB GCIXP1200FA GCIXP1200FB GCIXP1200FC 1 GCIXP1200GC GCIXP1200GA GCIXP1200GB GCIXP1200GC 1. Samples only. Figure 1. Package Marking (D0 Stepping) Pin 1 Specification Update Intel Stepping QDF Number QDF 310 GCIXP1200XX FPO# INTEL(M)(C)2001 xxxxxxxSz YWW PHILIPPINES ® IXP1200 Network Processor Identification Information ...
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... Intel IXP1200 Network Processor Errata Errata 1. SRAM Registers Reads of the SRAM_BOOT_CONFIG and SRAM_SLOWPORT_CONFIG registers return the Problem: two inner bytes out of order. SRAM_BOOT_CONFIG: Written as: BRWA BCEA BRWD BCED Read as: BRWA BRWD BCEA BCED SRAM_SLOWPORT_CONFIG: Written as: SRWA SCEA SRWD SCED Read as: SRWA SRWD SCEA SCED Bytes are read out of order ...
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... SDRAM Descriptor Pointer immed[tmp1, 0x1000] alu[DESC_ADDR,--,B,tmp1,>>1] ; issue DMA request pci_dma[DESC_ADDR, 0, any_queue] NoFix Status: Specification Update ® Intel IXP1200 Network Processor Errata O Inbound Queue pointers to determine 2 13 ...
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... Intel IXP1200 Network Processor Errata 7. SDRAM Memory Reference with SDRAM optimize_ mem Instruction Qualifier Due to an arbitration issue, when the SDRAM optimize_mem instruction qualifier is used Problem: possible that an SDRAM reference may not be serviced in a timely manner. This can occur if ALL memory references are to the same bank, AND some references are qualified with optimize_mem, AND the non-optimize_mem references consistently keep the Order Queue non-empty ...
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... Inability to meet the data setup time specification for memory devices. Implication: Buffer SCLK and SDCLK with a zero skew clock buffer such as a Cypress CY2309. Workaround: NoFix Status: Specification Update ® Intel IXP1200 Network Processor ) may be seen under heavy loading conditions. The maximum su Errata 15 ...
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... Intel IXP1200 Network Processor Errata 14. FDAT and FBE# Signals After Reset In Shared IX Bus mode, there may be a one cycle differential between when the master and slave Problem: devices come out of reset. For one cycle after reset, both devices may be driving the data bus high, FDAT[63:0], and the byte Implication: enable signals, FBE#[7:0] ...
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... Using prepend in 32-bit unidirectional IX Bus mode has unpredictable results. Implication: Only use the first longword of prepend. Disregard second longword. Workaround: Fixed Status: Specification Update ® Intel IXP1200 Network Processor Errata 17 ...
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... Intel IXP1200 Network Processor Errata 23. PCI CBE# Values on I/O Reads When the StrongARM* core accesses the PCI bus through an I/O read with transactions that are Problem: not in longword lengths, the CBE# field will have incorrect values. On data sizes less than a longword, incorrect data will be transferred. ...
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... IXP1200 to initial IX Bus Owner and Ready Bus Master Mode by writing RDYBUS_TEMPLATE_CTL[8]= recommended to perform this operation as quickly as possible after reset to minimize the length of time the IX Bus and Ready Bus float. NoFix Status: Specification Update ® Intel IXP1200 Network Processor Errata 19 ...
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... Intel IXP1200 Network Processor Errata 31. Tval max Timing Issues When Running at 66 MHz for all PCI Signals The PCI Local Bus Specification, Revision 2.2 specifies a maximum Signal Valid Delay (Tval) Problem: time of 6.0ns in Section 7.6.4.2. The IXP1200 guarantees a worst-case Tval maximum of 6.5 ns. ...
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... IXP1200_REG_READ(a,val) ((val) = *(volatile UINT32 *)(a)) #define IXP1200_REG_WRITE(a,val) (*(volatile UINT32 *)(a) = (val)) #define TANDSBIT 0x0001 #define COREBIT int tandsInit() { IXP1200_REG_WRITE(WORD_ADDR, 0); IXP1200_REG_WRITE(DATA_ADDR, 0); return 0; } int tandsLoop(int n) { int i=0; int j; int xfer; for (; n > 0; n--) { while (1) { IXP1200_REG_WRITE(SET_ADDR, COREBIT); IXP1200_REG_READ(WORD_ADDR, xfer); Specification Update 0x0002 ® Intel IXP1200 Network Processor Errata 21 ...
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... Intel IXP1200 Network Processor Errata if (xfer == COREBIT) if (xfer != (COREBIT | TANDSBIT taskDelay(1 end while got test-and-set */ /* get data */ /* Place code here to access locked resource */ /* release test-and-set */ IXP1200_REG_WRITE(CLEAR_ADDR, COREBIT); } return i + 0x10000 Filename: tands.uc ; test-and-set code for Microengines #define TANDSBIT 0x01 #define COREBIT ...
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... PCI enumeration code to a value of 0000. The StrongARM* core can poll this register and rewrite correct value after BIOS or a driver writes Workaround: this register. Fixed Status: Specification Update ® Intel IXP1200 Network Processor Errata 23 ...
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... Intel IXP1200 Network Processor Errata 35. PCI CSR (Control and Status Register) Access StrongARM* core writes to any of the registers in the PCI Unit can get blocked if the write Problem: coincides in time with a PCI Master-to-CSR access. The StrongARM* core does the write operation, but the write data may not be written to the register. ...
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... I2O Outb Post List Count (I2O_OUTB_PLIST_CNT) I2O Inb Post List Count (I2O_INB_PLIST_CNT) SA Control (SA_CONTROL) PCI Address Extension (PCI_ADDR_EXT) Specification Update Register Name 100 120 124 128 12c 130 134 138 13c 140 ® Intel IXP1200 Network Processor Offset Type Side Effects (See below W1S RW/W1C Y ...
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... Intel IXP1200 Network Processor Errata Doorbell PCI Mask (DBELL_PCI_MASK) Doorbell SA Mask (DBELL_SA_MASK) IRQ_Status (IRQ_STATUS) IRQ_Raw_Status (IRQ_RAW_STATUS) IRQ_Enable (IRQ_ENABLE) IRQ_Enable_Set (IRQ_ENABLE_SET) IRQ_Enable_Clear (IRQ_ENABLE_CLEAR) IRQ_Soft (IRQ_SOFT) FIQ_Status (FIQ_STATUS) FIQ_Raw_Status (FIQ_RAW_STATUS) FIQ_Enable (FIQ_ENABLE) FIQ_Enable_Set (FIQ_ENABLE_SET) FIQ_Enable_Clear (FIQ_ENABLE_CLEAR) FIQ_Soft (FIQ_SOFT) Timer 1 Load (TIMER_1_LOAD) Timer 1 Value (TIMER_1_VALUE) ...
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... The Mailbox registers are RW and have no side effects. The assumption made is that ownership of each mailbox by either the StrongARM* core or PCI Host is either statically defined in the application, or coordinated by some other means such as Doorbells. Fixed Status: Specification Update ® Intel O Outbound Post List Count 2 O Inbound Post List Count (I2O_INB_PLIST_CNT) 2 IXP1200 Network Processor Errata ...
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... Intel IXP1200 Network Processor Errata 36. Inoperative PCI_OUT_INT_MASK Register The IXP1200 Network Processor PCI_OUT_INT_MASK register is not functional. This register is Problem: intended to prevent the IXP1200 from asserting pci_irq_l. A write to the PCI_OUT_INT_MASK register does not change the value of the register. A read of the PCI_OUT_INT_MASK register returns the value of the PCI_CAP_PTR register ...
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... It is recommended that the software programs not use the SRAM[WRITE_UNLOCK,…,ref_cnt] command with a ref_cnt > more than one long word needs to be written to memory, the software should use the workarounds described below. Specification Update ® Intel IXP1200 Network Processor Errata 29 ...
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... Intel IXP1200 Network Processor Errata Two workarounds have been developed and are described below: Workaround: 1. Break the SRAM[WRITE_UNLOCK,..., ref_cnt] instruction into a SRAM[write, …, ref_cnt] and SRAM[WRITE_UNLOCK,..., 1] pair. Workaround 1 requires two Microengine Instruction Control Store locations, but results in one extra SRAM bus write cycle possible to eliminate the extra bus cycle by suitably modifying the transfer register, address, and, ref_cnt fields, but may result extra Microengine instructions needed to compute the address ...
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... NOT grant any command that isn’t intended for the high priority queue. Using the optimize_mem token on SDRAM references may freeze microengines Implication: Don’t use opt_mem queue with SDRAM references Workaround: Fixed Status: Specification Update ® Intel IXP1200 Network Processor sdram[ ], optimize_mem Errata 31 ...
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... Intel IXP1200 Network Processor Errata 41. SA1200 Software Reset PCI-SA1200 Reset register does not function as specified. Problem: Three mechanisms are used to reset the IXP1200: • Two hardware inputs (PCI_RST# and RESET_IN# ) • One software reset (SW) via the IXP1200_RESET register. Problems have been observed in attempting to reset the IXP1200 via the PCI_RST# input or the IXP1200_RESET register (SW reset) ...
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... When this bit is read, the IXP1200 incorrectly indicates that it is not capable of operating at 66 Implication: MHz as defined in the PCI Local Bus Specification, Revision 2.2. Do not use this bit for determining the maximum operating frequency of the IXP1200’s PCI bus. Workaround: Status: NoFix. Specification Update ® Intel IXP1200 Network Processor Errata 33 ...
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... Intel IXP1200 Network Processor Specification Changes Specification Changes 1. SRAM Bus Signal Timing Parameters The maximum clock to data output valid delay (T specified as 4.0 ns. The new T The maximum clock to control outputs valid delay (T originally specified as 4.0 ns. The new T The minimum data input setup time before SCLK for pipelined SRAMs (T operation was originally specified as 3 ...
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... The minimum Cycle Low Time (T The new T value 4.02 ns. low Specification Update Intel ) for 232 MHz operation was originally specified as 8.6 ns. The cyc ) for 232 MHz operation was originally specified as 4.6 ns. high ) for 232 MHz operation was originally specified as 4.6 ns. ...
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... Intel IXP1200 Network Processor Specification Clarifications Specification Clarifications 1. Command Bus Arbitration Policy Clarification of the Command Bus Arbiter operation. Issue: Information contained in the IXP1200 Network Processor Family Hardware Reference Manual incorrectly described the arbiter operation. The Command Bus Arbiter arbitrates between the six Microengines to determine which Command FIFO will be serviced next ...
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... Figure 2. Results for DMA Receive in Big Endian Mode - Unaligned Transfer Specification Update ® Intel IXP1200 Network Processor Specification Clarifications 37 ...
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... Intel IXP1200 Network Processor Documentation Changes Documentation Changes None for this revision of the specification update. 38 Specification Update ...