GCIXP1250BC Intel, GCIXP1250BC Datasheet
GCIXP1250BC
Specifications of GCIXP1250BC
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GCIXP1250BC Summary of contents
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... Intel IXP1250 Network Processor Specification Update March 2004 Notice: The IXP1250 may contain design defects or errors known as errata. Characterized errata that may cause the IXP1250’s behavior to deviate from published specifications are documented in this specification update. Part Number: 278377-006 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Contents Preface ...............................................................................................................................................5 Summary Table of Changes...............................................................................................................7 Identification Information................................................................................................................10 Errata................................................................................................................................................11 Specification Changes......................................................................................................................21 Specification Clarifications..............................................................................................................23 Documentation Changes ..................................................................................................................25 Specification Update ® IXP1250 Network Processor Intel iii ...
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... IXP1250 Network Processor Intel iv Specification Update ...
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... This document may also contain information that was not previously published. Related Documents IXP1250 Network Processor Datasheet IXP1200 Network Processor Family Hardware Reference Manual Specification Update ® Intel IXP1250 Network Processor Title Preface Part Number 278371 278303 ...
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... Intel IXP1250 Network Processor Preface Nomenclature Errata are design defects or errors. These may cause the published (component, board, system) behavior to deviate from published specifications. Hardware and software designed to be used with any component, board, and system must consider all errata documented. ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the IXP1250 Network Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following ...
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... Intel IXP1250 Network Processor Summary Table of Changes Errata No Specification Changes Steppings No Steppings Page Status B0 – – NoFix X 11 NoFix X 11 NoFix X 12 NoFix X 12 NoFix X 12 NoFix X 12 NoFix X 13 NoFix X 13 NoFix 15 Fixed 16 Fixed X 16 NoFix 16 Fixed 16 Fixed 16 Fixed ...
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... Specification Clarifications Steppings No Documentation Changes No. Page Specification Update Page SPECIFICATION CLARIFICATIONS – – 23 SRAM Unlocks and Write Unlocks 23 Maximum Number of Chain_Ref Instructions 23 DMA Receive in Big Endian Mode DOCUMENTATION CHANGES None for this release ® Intel IXP1250 Network Processor Summary Table of Changes 9 ...
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... Intel IXP1250 Network Processor Identification Information Identification Information Markings Product Name GCIXP1250AA GCIXP1250AB GCIXP1250BC GCIXP1250BA GCIXP1250BB GCIXP1250BC GCIXP1250BAT GCIXP1250BAT 1. Samples only. Figure 1. Package Marking Pin 1 10 Stepping QDF Number 1 A0 Q223 1 A0 Q224 1 B0 Q258 Q277 GCIXP1250xx FFFFFFFF INTEL M C 2001 ...
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... For example, the address of a Descriptor Pointer located at SDRAM address 0x1000 should be right-shifted 1 bit with the resulting operand value being 0x0800, as follows: ; fix address of SDRAM Descriptor Pointer immed[tmp1, 0x1000] alu[DESC_ADDR,--,B,tmp1,>>1] ; issue DMA request pci_dma[DESC_ADDR, 0, any_queue] NoFix Status: Specification Update ® Intel IXP1250 Network Processor Errata 11 ...
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... Intel IXP1250 Network Processor Errata 4. Clock Setup Time Because the SRAM and SDRAM setup times are directly related to the loading of SCLK and Problem: SDCLK, excessive setup times (T value of T for both memory interfaces is 7.5 ns. su Inability to meet the data setup time specification for memory devices. ...
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... SRAM unit. Because the commands arrive at the SRAM unit from different Microengine threads impossible to determine if a software using this mode of command is prone to failure, or, when it will fail. The exact symptoms observed by the user will depend on the system software design and implementation. Specification Update ® Intel IXP1250 Network Processor Errata 13 ...
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... Intel IXP1250 Network Processor Errata For example, if the thread waits for the completion of the write_unlock command that gets dropped (either using the ctx_swap optional token, or, the sig_done optional token and ctx_arb[SRAM] command), then that thread will hang indefinitely. Further, the write to the memory location will not complete leading to data corruption problems ...
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... SDRAM_CSR register are not functional. They will always read back as "0". The device cannot detect what block initiated the SDRAM read that resulted in an ECC error. Implication: Note: The error will be corrected if EN_ECC_GEN is enabled (bit 3). None. Workaround: Fixed Status: Specification Update ® Intel IXP1250 Network Processor Errata 15 ...
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... Intel IXP1250 Network Processor Errata 11. PCI_OUT_INT_MASK Register Bits Not Readable PCI Out Interrupt Mask register at 34h. The register is write only and cannot be read back. Problem: The mask is operational, but the only way to test generating I Implication: PCI, writing 1 to this register, and then checking if subsequent interrupts to PCI are masked. ...
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... The Parity bit in the PCI interface is not set correctly. The Parity error indication bit in the PCI_STATUS register is correct. Bad parity. Implication: Use the register parity error indication in the PCI_STATUS register. Workaround: Fixed Status: Specification Update ® Intel IXP1250 Network Processor Errata 17 ...
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... Intel IXP1250 Network Processor Errata 19. Find Bit Find Bit works on the software model but not in the actual hardware. The operation returns zero Problem: when a non-zero result is expected. ; Demonstration of find_bset_with_mask erratum ; ; The data register is loaded with all 1’s ; Then find_bset_with_mask with a mask of 0x10, ...
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... TFIFO using the TFIFO[write] command. Example A Original code: // Format indirect_ref for ref_cnt, tfifo_addr, and byte_align alu[ind, refCnt,-,1] alu[ind, --, B, ind, <<16] alu[ind, ind, OR, 1, <<20] alu[ind, ind, OR, byte_align, <<12] alu[ind, ind, OR, tfifo_addr, <<4] sdram_crc[t_fifo_wr, Specification Update --, dramBufferAddr, dramBufferOffset, 1], indirect_ref, chained_ref ® Intel IXP1250 Network Processor Errata 19 ...
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... Intel IXP1250 Network Processor Errata Updated code: In the following code, dram_crc_tfifo_wr , crc_dram , and merge_data are macros that must be written by the user. // Start formatting of indirect_ref with tfifo_addr alu[ind,--, B, fifoAddr, <<4] // First check if dram address will cross burst // boundary. In this example, burst length = 8 ...
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... MHz operation was originally specified as 8.6 ns. The cyc ) for 232 MHz operation was originally specified as 4.6 ns. high ) for 232 MHz operation was originally specified as 4.6 ns. low ® Intel IXP1250 Network Processor Specification Changes ) value for 232 MHz sup value is 3.10 ns. sup ) value for 232 MHz operation was value is 3 ...
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... Intel IXP1250 Network Processor Specification Changes 5. SDRAM SDCLK AC Parameters The minimum Cycle Time (T new T value is 8.62 ns. cyc The minimum Cycle High Time (T The new T value is 4.02 ns. high The minimum Cycle Low Time (T The new T value 4.02 ns. low 22 ) for 232 MHz operation was originally specified as 8.6 ns. The cyc ) for 232 MHz operation was originally specified as 4 ...
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... The documentation does not clearly describe the PCI receive operation when Big Endian Data In is Issue: set. The fact that byte swapping occurs before the data is aligned was not clearly articulated. The clarification in Figure 2 Specification Update will eliminate all ambiguities. ® Intel IXP1250 Network Processor Specification Clarifications 23 ...
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... Intel IXP1250 Network Processor Specification Clarifications Figure 2. Results for DMA Receive in Big Endian Mode - Unaligned Transfer 24 Specification Update ...
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... Documentation Changes None for this version of the specification update. Specification Update ® Intel IXP1250 Network Processor Documentation Changes 25 ...
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... Intel IXP1250 Network Processor Documentation Changes 26 Specification Update ...