Z8018010VSC00TR Zilog, Z8018010VSC00TR Datasheet - Page 58
Z8018010VSC00TR
Manufacturer Part Number
Z8018010VSC00TR
Description
IC Z180 MPU 68PLCC
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018010VSC00TR
Processor Type
Z180
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Timer Data Register
Timer Data Register
PS014004-1106
Timer Data Register Channel 1L
Timer Data Register Channel 1H
Break Detect (bit 1)—The receiver sets this
character with a Framing Error becomes the oldest character in the
cleared when software writes a
IOSTOP
Send Break (bit 0)—If this bit and bit
to send a break condition. The duration of the break is under software control (one of the
PRTs
serial output of the transmitter.
Mnemonic TMDR1L:14H
Mnemonic TMDR1H: 15H
or
CTCs
mode, and for
can be used to time it). This bit resets to
Figure 43. Timer Data Register Channel 1L
Figure 44. Timer Data Register Channel 1H
7
7
6
6
ASCIO
5
5
if the
0
4
4
to the
DCD0
3
3
Timer Data
Timer Data
EFR
2
are both
pin is auto-enabled and is negated (High).
2
2
bit in
READ-ONLY
1
1
CNTLA
1
, the transmitter holds the
0
0
0
, in which state
register, also by
bit to
1
RxFIFO
Microprocessor Unit
when an all-zero
TXA
. The bit is
RESET
carries the
TXA
Architecture
, by
pin Low
Z80180
52
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