Z8018010FEC Zilog, Z8018010FEC Datasheet - Page 79

• Manufacturer Part Number: Z8018010FEC
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8018010FEC

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2 bit
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Height: 2.8 mm
• Length: 20 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Operating Control OMCR: I/O Address = 3Eh)
PS014004-1106
A
0
–A
18
Control Register (OMCR) can be programmed to select between certain differences between
the Z80 and the 64180.
M1E (M1 Enable)—This bit controls the
during reset.
When
acknowledge cycle, and the first machine cycle of the
On the Z80180, this choice makes the processor fetch a
when fetching a
are not fully Z80-timing compatible, but are compatible with the on-chip CTCs.
When
fetching a
instruction using fully Z80-compatible cycles that include driving
some external Z80 peripherals may require properly decoded
MREQ
D
(A
0
–D
Figure 76. Operating Control Register (OMCR: I/O Address = 3Eh
RD
M1
19
ST
φ
)
7
M1E = 1
MIE = 0
T
1
RETI
Figure 77. RETI Instruction Sequence with MIE=0
T
D7
2
, the processor does not drive
, the
PC
EDh
instruction one time only with normal timing, the processor refetches the
RETI
T
D6 D5 —
3
M1
T
1
from zero-wait-state memory, uses three clock machine cycles which
output is asserted Low during the opcode fetch cycle, the
T
2
4Dh
T
— — — —
3
PC+1
T
I
T
I
T
I
M1
M1
T
Reserved
IOC (R/W)
1
M1TE (W)
M1E (R/W)
output and is set to a
Low during instruction fetch cycles. After
T
2
EDh
T
PC
NMI
3
RETI
T
acknowledge.
I
instruction one time only, and
RETI
T
1
M1
T
2
instruction.
Microprocessor Unit
1
PC+1
4Dh
Low. As a result,
T
3
T
I
Architecture
INT0
Z80180
73