EZ80L92AZ020SC Zilog, EZ80L92AZ020SC Datasheet - Page 187

• Manufacturer Part Number: EZ80L92AZ020SC
• Description: IC WEBSERVER 20MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3168; EZ80L92AZ020SC

PS013014-0107
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See
Table 105. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI
Register Read-Only Address Space)
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
ZDI_RD_U
Bit
Reset
CPU Access
Note: R = Read-only.
Bit
Position
7
ZDI_BUSAcK_En
6
ZDI_BUS_STAT
[5:0]
00h–FFh Values read from the memory location as requested by
000000 Reserved.
Value
Value
0
1
0
1
R
7
0
the ZDI Read Control register during a ZDI Read
operation. The 24-bit value is supplied by {ZDI_RD_U,
ZDI_RD_H, ZDI_RD_L}.
Description
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R
2
0
ZiLOG Debug Interface
eZ80L92 MCU
R
1
0
Table
105.
R
0
0
181