IDT79RC32V332-133DHI IDT, Integrated Device Technology Inc, IDT79RC32V332-133DHI Datasheet - Page 10

• Manufacturer Part Number: IDT79RC32V332-133DHI
• Description: IC PROC 32BIT CPU 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V332-133DHI

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32V332-133DHI

IDT 79RC32332
ejtag_pcst[2:0]
ejtag_debugboot
ejtag_tms
Debug Signals
debug_cpu_dma_n
debug_cpu_ack_n
debug_cpu_ads_n
debug_cpu_i_d_n
Name
Type
Input
Input
I/O
I/O
I/O
I/O
I/O
Status
Reset
State
Z
Z
Z
Z
Z
Capability
Strength
Drive
Low
Low
Low
Low
Low
—
—
EJTAG PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
Alternate function: modebit[2:0].
EJTAG DebugBoot Requires an external pull-down.
The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the
end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe
without having the external memory working. This input signal is level sensitive and is not latched inter-
nally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
EJTAG Test Mode Select Requires an external pull-up.
The ejtag_tms is sampled on the rising edge of jtag_tck.
Debug CPU versus DMA Negated
De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac-
tion was generated from the CPU.
Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction
was generated from DMA.
Alternate function: modebit[6].
Debug CPU Acknowledge Negated
Indicates either a data acknowledge to the CPU or DMA.
Alternate function: modebit[4].
Debug CPU Address/Data Strobe Negated
Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus
has the current block address.
Alternate function: modebit[5].
Debug CPU Instruction versus Data Negated
Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a
CPU or DMA data transaction.
De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is
a CPU instruction transaction.
Alternate function: modebit[3].
Table 1 Pin Descriptions (Part 6 of 6)
10 of 30
Description
May 4, 2004