IDT79RC32V332-133DHI IDT, Integrated Device Technology Inc, IDT79RC32V332-133DHI Datasheet - Page 6

• Manufacturer Part Number: IDT79RC32V332-133DHI
• Description: IC PROC 32BIT CPU 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V332-133DHI

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32V332-133DHI

IDT 79RC32332
mem_wait_n
mem_245_oe_n
mem_245_dt_r_n
output_clk
PCI Interface
pci_ad[31:0]
pci_cbe_n[3:0]
pci_par
pci_frame_n
pci_trdy_n
pci_irdy_n
pci_stop_n
pci_idsel_n
pci_perr_n
pci_serr_n
pci_clk
pci_rst_n
pci_devsel_n
Name
Output
Output
Output cpu_mas
Type
Open-
collec-
Input
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
tor
Status
Reset
State
terclk
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
Capability
Strength
Drive
High
High
Low
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
—
—
—
—
Memory Wait Negated Requires an external pull-up.
SRAM/IOI/IOM modes: Allows external wait-states to be injected during the last cycle before data is sam-
pled.
DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.
Alternate function: sdram_wait_n.
Memory FCT245 Output Enable Negated
Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to
a memory or I/O bank.
Memory FCT245 Direction Xmit/Rcv Negated Recommend an external pull-up.
Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.
Output Clock
Optional clock output.
PCI Multiplexed Address/Data Bus
Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus
Master during writes; or the Data is driven by the Bus Slave during reads.
PCI Multiplexed Command/Byte Enable Bus
Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable
Negated Bus driven by the Bus Master during the data phase(s).
PCI Parity
Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven
by the Bus Slave during the Read Data phase.
PCI Frame Negated
Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates
the last datum.
PCI Target Ready Negated
Driven by the Bus Slave to indicate the current datum can complete.
PCI Initiator Ready Negated
Driven by the Bus Master to indicate that the current datum can complete.
PCI Stop Negated
Driven by the Bus Slave to terminate the current bus transaction.
PCI Initialization Device Select
Uses pci_req_n[2] pin. See the PCI subsection.
PCI Parity Error Negated
Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.
System Error Requires an external pull-up.
Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or
any other system error.
PCI Clock
Clock for PCI Bus transactions. Uses the rising edge for all timing references.
PCI Reset Negated
Host mode: Resets all PCI related logic.
Satellite mode: Resets all PCI related logic and also warm resets the 32332.
PCI Device Select Negated
Driven by the target to indicate that the target has decoded the present address as a target address.
Table 1 Pin Descriptions (Part 2 of 6)
6 of 30
Description
May 4, 2004