IDT79RV4650-150DP IDT, Integrated Device Technology Inc, IDT79RV4650-150DP Datasheet - Page 11

• Manufacturer Part Number: IDT79RV4650-150DP
• Description: IC MPU 64BIT W/DSP 150MHZ 208QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RV4650-150DP

• Processor Type: RISC 64-Bit
• Speed: 150MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RV4650-150DP

Pin Descriptions
IDT79RC4650™
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4650. Pins marked with one asterisk are active when low.
System interface:
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
Clock/control interface:
MasterClock
V
V
Interrupt interface:
Int*(5:0)
NMI*
CC
SS
P
P
Pin Name
Input
Output
Input
Input
Input
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Input
Input
Type
External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command
or data identifier on the SysCmd bus.
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
Reserved system command/data identifier bus parity
For the RC4650 this signal is unused on input and zero on output.
Master clock
Master clock input used as the system interface reference clock. All output timings are relative to this input
clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during
boot initialization.
Quiet VCC for PLL
Quiet V
Quiet VSS for PLL
Quiet V
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
CC
SS
for the internal phase locked loop.
for the internal phase locked loop.
11 of 25
Description
April 10, 2001