IDT79RV4650-150DP IDT, Integrated Device Technology Inc, IDT79RV4650-150DP Datasheet - Page 9

• Manufacturer Part Number: IDT79RV4650-150DP
• Description: IC MPU 64BIT W/DSP 150MHZ 208QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RV4650-150DP

• Processor Type: RISC 64-Bit
• Speed: 150MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RV4650-150DP

Boot-Time Options
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
information to be kept in a low-cost EPROM; alternatively the twenty-or-
so bits could be generated by the system interface ASIC or a simple
PAL.
V
bits. After initialization is complete, the processor continues to drive the
serial clock output, but no further initialization bits are read.
Boot-Time Modes
presented to the processor when V
Power Management
This is the standby mode and it can be used to reduce the power
consumption of the internal core of the CPU. The standby mode is
entered by executing the WAIT instruction with the SysAD bus idle and
is exited by any interrupt.
Standby Mode Operation
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
Entering Standby Mode
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, and some of the input pins
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. If
the conditions are not correct when the WAIT instruction finishes the W
pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP.
nally generated timer interrupt, will cause the CPU to exit Standby
Mode.
CCOK
IDT79RC4650™
The following is a list of the supported external requests:
Fundamental operational modes for the processor are initialized by
To initialize all fundamental, operational modes, immediately after the
The boot-time serial mode stream is defined in Table 5. Bit 0 is the bit
CP0 is also used to control the power management for the RC4650.
The RC4650 provides a means to reduce the amount of power
Executing the WAIT instruction enables interrupts and enters
Once the CPU is in Standby Mode, any interrupt, including the inter-
◆
◆
Read Response
Null
signal is asserted, the processor reads a serial bit stream of 256
CCOK
is asserted; bit 255 is the last.
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Thermal Considerations
thermal properties of high-speed processors. The RC4650 is packaged
using cavity down packaging in a 208-pin QFP (DP). The QFP package
allows for an efficient thermal transfer between the die and the case.
range of 0°C to +85°C for commercial temperature parts and in a case
temperature range of -40°C to +85°C for industrial temperature parts.
The type of package, speed (power) of the device, and airflow conditions
affect the equivalent ambient temperature conditions that will meet this
specification. The equivalent allowable ambient temperature, T
The RC4650 utilizes special packaging techniques to improve the
The R4650 and the RV4650 are guaranteed in a case temperature
255..15
14..13
11
12
10..9
8
7..5
4..1
0
Mode bit
Table 5 Boot-time mode stream
Must be zero
Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slowest)
Disable the timer interrupt on Int[5]
0 → 64-bit system interface
1 → 32-bit system interface
00 → RC4000 compatible
01 → reserved
10 → pipelined writes
11 → write re-issue
0 → Little endian
1 → Big endian
Clock multiplier:
0 → 2
1 → 3
2 → 4
3 → 5
4 → 6
5 → 7
6 → 8
7 reserved
Writeback data rate:
64-bit
0 → ∆
1 → DDx
2 → DDxx
3 → DxDx
4 → DDxxx
5 → DDxxxx
6 → DxxDxx
7 → DDxxxxxx
8 → DxxxDxxx
9-15 reserved
Reserved (must be zero)
Description
32-bit
0 → Ω
1 → WWx
2 → WWxx
3 → WxWx
4 → WWxxx
5 → WWxxxx
6 → WxxWxx
7 → WWxxxxxx
8 → WxxxWxxx
9-15 reserved
April 10, 2001
A
, can be