MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 13

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

13
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES: 1.
NUM
31
48
58A
29A
36
47
56
58
29
30
32
33
34
35
38
39
44
52
53
55
2,5
2,3
7
5
4
7
7
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
AS, LDS, UDS Negated to Data-In High Impedance (Read)
AS, LDS, UDS Negated to BERR Negated
DTACK Asserted to Data-In Valid (Setup Time on Read)
HALT and RESET Input Transition Time
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
BG Width Negated
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
BERR Asserted to DTACK Asserted
Data-In Hold from Clock High
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
BR Negated to AS, LDS, UDS, R/W Driven
BR Negated to FC Driven
2.
3.
4.
5.
6.
7.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
Actual value depends on clock period.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
When AS and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
CHARACTERISTIC
Freescale Semiconductor, Inc.
For More Information On This Product,
M68000 USER’S MANUAL ADDENDUM
Go to: www.freescale.com
MIN
1.5
1.5
1.5
1.5
20
20
10
—
—
—
—
—
0
0
0
0
5
0
0
1
10MHz
MAX
150
150
3.5
3.5
65
35
35
55
55
—
—
—
—
—
—
—
—
—
—
—
MIN
1.5
1.5
1.5
1.5
10
10
10
—
—
—
—
—
0
0
0
0
5
0
0
1
16MHz
MAX
150
3.5
3.5
90
50
30
30
50
50
—
—
—
—
—
—
—
—
—
—
—
MIN
1.5
1.5
1.5
1.5
—
10
10
—
—
—
—
0
0
0
0
5
0
0
0
1
20MHz
MAX
150
MOTOROLA
3.5
3.5
—
75
—
42
25
25
42
—
42
—
—
—
—
—
—
—
—
UNIT
Clks
Clks
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns