MPC8313CVRADDB Freescale Semiconductor, MPC8313CVRADDB Datasheet - Page 43

• Manufacturer Part Number: MPC8313CVRADDB
• Description: MPU POWERQUICC II PRO 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CVRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 267MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8313E-RDB
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 2.5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM/Flash
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 30
It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock
input’s DC requirement.
9.2.4
The clock driver selected should provide a high quality reference clock with low-phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 40
Freescale Semiconductor
At recommended operating conditions with XV
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Clock Driver
Single-Ended CLK
Driver Chip
describes some AC parameters for SGMII protocol.
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
MPC8313E PowerQUICC
Parameter
Table 40. SerDes Reference Clock Common AC Parameters
Figure 30. Single-Ended Connection (Reference Only)
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
DD_SRDS1
100 Ω Differential PWB Trace
™
or XV
II Pro Processor Hardware Specifications, Rev. 3
DD_SRDS2
Rise edge rate
Fall edge rate
= 1.0 V ± 5%.
Symbol
V
V
IH
IL
SD n _REF_CLK
SD n _REF_CLK
+200
Min
1.0
1.0
—
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
MPC8313E
–200
Max
4.0
4.0
—
SerDes Refer.
CLK Receiver
Unit
V/ns
V/ns
mV
mV
Notes
2, 3
2, 3
2
2
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