MPC8245TZU266D Freescale Semiconductor, MPC8245TZU266D Datasheet - Page 24

• Manufacturer Part Number: MPC8245TZU266D
• Description: IC MPU 32BIT 266MHZ PPC 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8245TZU266D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 266MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 1.7V To 2.1V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
Figure 14
24
Notes:
1. All PCI signals are measured from GV
2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL,
4. To meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the MPC8245
Num
14b
signal in question for 3.3 V PCI signaling levels. See
memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See
PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.
has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial
value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on
these two signals are inverted and stored as the initial settings of PCI_HOLD_DEL = PMCR2[5, 4] (power management
configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of
PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL
value of the PMCR2 configuration register.
sys_logic_clk to output high impedance (for all others)
provides the AC test load for the MPC8245.
Output
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Table 11. Output AC Timing Specifications (continued)
Figure 14. AC Test Load for the MPC8245
Characteristic
Z
DD
0
= 50 Ω
/2 of the rising edge of PCI_SYNC_IN to 0.285 × OV
Output Measurements are Made at the Device Pin
Figure 15
Figure
Figure
shows the PCI_HOLD_DEL effect on output valid and hold times.
11.
12.
R
L
= 50 Ω
OV
GV
Min
DD
DD
—
/2 for PCI
/2 for Memory
DD
Max
4.0
or 0.615 × OV
Freescale Semiconductor
Unit
ns
DD
of the
Notes
2