MPC8343CVRAGDB Freescale Semiconductor, MPC8343CVRAGDB Datasheet - Page 43

IC MPU PWRQUICC II 620-PBGA

MPC8343CVRAGDB

Manufacturer Part Number
MPC8343CVRAGDB
Description
IC MPU PWRQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8343CVRAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
For Use With
CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8343CVRAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 42
Figure 29
Freescale Semiconductor
Input hold from clock
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
2. The symbols for timing specifications follow the pattern of t
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
5. Input timings are measured at the pin.
Clock to output valid
Output hold from clock
Clock to output high impedance
Input setup to clock
Input hold from clock
Notes:
1. The symbols for timing specifications follow the pattern of t
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
4. Input timings are measured at the pin.
description of M66EN.
and t
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
to the high (H) state or setup time. Also, t
high (H) relative to the frame signal (F) going to the valid (V) state.
component pin is less than or equal to the leakage current specification.
and t
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
to the high (H) state or setup time. Also, t
high (H) relative to the frame signal (F) going to the valid (V) state.
component pin is less than or equal to the leakage current specification.
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
provides the PCI AC timing specifications at 33 MHz.
provides the AC test load for PCI.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Parameter
Parameter
Table 41. PCI AC Timing Specifications at 66 MHz
Output
Table 42. PCI AC Timing Specifications at 33 MHz
PCRHFV
PCRHFV
Figure 29. PCI AC Test Load
Z
0
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
= 50 Ω
Symbol
Symbol
t
t
t
PCKHOV
t
t
t
PCKHOX
PCKHOZ
for outputs. For example, t
for outputs. For example, t
PCIXKH
PCIVKH
PCIXKH
(first two letters of functional block)(signal)(state)(reference)(state)
(first two letters of functional block)(signal)(state)(reference)(state)
2
1
R
L
Min
Min
3.0
= 50 Ω
0
2
0
1
PCIVKH
PCIVKH
(continued)
OV
DD
symbolizes PCI timing (PC) with
symbolizes PCI timing (PC) with
Max
Max
11
14
/2
SYS
SYS
, reference (K) going
, reference (K) going
Unit
Unit
ns
ns
ns
ns
ns
ns
for inputs
for inputs
Notes
Notes
3, 5
2, 3
2, 4
2, 4
2
2
PCI
43

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