MPC8349EVVAJDB Freescale Semiconductor, MPC8349EVVAJDB Datasheet - Page 33

• Manufacturer Part Number: MPC8349EVVAJDB
• Description: IC MPU PWRQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8349EVVAJDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 16
Freescale Semiconductor
At recommended operating conditions with LV
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
and t
timing (MD) for the time t
t
relative to the t
is used with the appropriate letter: R (rise) or F (fall).
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
333 MHz, the delay is 58 ns).
MDDVKH
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
Parameter/Condition
shows the MII management AC timing diagram.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
MDC
(Output)
(Input)
MDIO
MDIO
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
MDC
Table 34. MII Management AC Timing Specifications (continued)
MDC
Figure 16. MII Management Interface Timing Diagram
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
t
MDCH
DD
t
is 3.3 V ± 10% or 2.5 V ± 5%.
MDDVKH
t
MDC
t
MDKHDX
Symbol
t
MDHF
1
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MDCF
Min
—
t
MDDXKH
t
MDCR
Ethernet: Three-Speed Ethernet, MII Management
Typ
—
MDKHDX
Max
symbolizes management data
10
Unit
ns
for inputs
Notes
—
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