MPC860ENCVR50D4 Freescale Semiconductor, MPC860ENCVR50D4 Datasheet - Page 3

• Manufacturer Part Number: MPC860ENCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC860ENCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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The following list summarizes the key MPC860 features:
Freescale Semiconductor
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Features
Embedded single-issue, 32-bit core (implementing the Power Architecture technology) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch without conditional execution.
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs
— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual
— Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes to 256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture.
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
address spaces and 16 protection groups
devices
caches are two-way, set-associative with 128 sets.
two-way, set-associative with 128 sets.
cache blocks.
algorithm, and are lockable on a cache block basis.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Table
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Features
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