MC68MH360AI25L Freescale Semiconductor, MC68MH360AI25L Datasheet - Page 42

• Manufacturer Part Number: MC68MH360AI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
In Figure 2-5, each SCC has its own pointer, Rx_S_PTR_2 and Rx_S_PTR_3, addressing
SCC2’s time slot assignment table. This table only needs to be present once in one of the
SCC2’s global parameter area. Rx_S_PTR_2 points to the start of the table, address SCC
base + 20. The 16 logical channels from SCC2 are located in the first 16 entries of the table.
The entry for logical channel 30 has the wrap bit (W) set, causing the CPM to wrap back
to logical channel 0 on reception of the next byte routed to SCC2. Rx_S_PTR_3 addresses
SCC base + 40, the start of the 16 entries for SCC3. The entry for logical channel 31 has
the wrap bit (W) set, causing the CPM to wrap back to logical channel 1 on reception of the
next byte routed to SCC3. Each entry within the table has a channel pointer to a logical
channel. It is important that different SCCs do not point to the same logical channel.
The TSATTx is also located in SCC2’s parameter RAM. This means that the area reserved
for the TSA tables in SCC3’s parameter RAM is free for alternative use.
A second scenario is depicted in Figure 2-6. A 4.096-Mbps TDM link is fed directly into
the TSA. Again, within the SI RAM, the even channels (byte-wide) are muxed to SCC3 and
the odd channels are muxed to SCC2. This arrangement is used to spread the load over two
SCCs. Another reason this method may be used is to facilitate separate routing for the Rx
and Tx logical channels. This requires two 64-entry tables that require 256 bytes, but only
128 bytes are allocated in the parameter RAM of an SCC for time slot assignment tables.
In this case, the Rx table is located in SCC2’s parameter RAM, and the TX table is located
in SCC3’s parameter RAM, making most efficient use of memory.
Changes on the fly are easily accomplished by setting or clearing the valid bit for each time
slot. Changes to the mask bits can also be made on the fly. This does not cause any problems
to the QMC microcode itself, but may cause protocol errors on the channel in question
depending on when this change is done.
It is possible to have a time slot assignment table for every SCC in its corresponding RAM
page and have all of the TDM routed to the different SCCs. This gives the user a very
flexible system that can be changed on the fly without disconnecting the TDM interface. In
this case the user must ensure that no collisions occur on the transmit lines from several
SCCs.
QMC Supplement
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