MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 554

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
are provided in Figure 12-10. The most important differences occur in the
The structure of this memory bank is very similiar to the 2-1-1-1 memory
The data flip-flops allow the long words out of the memory to be pipelined
such that setup and hold times are easier to satisfy. The memory devices
are generating the next long word of data even before the MC68030 has
Another benefit of the slower cycle is a relaxed timing requirement for the
enable inputs of the SRAMs. Although Figure 12-15 has all the SRAM chip
enables grounded, the timing in this design will be preserved if the memory's
The flip-flop connected to the TERM signal serves two purposes: first, the
TERM signal is delayed at the beginning of the cycle to insert the wait state
for the first long word, and second, the burst address generator is also pre-
vented from incrementing the long word base address until the first long-
word has been latched by the 74F374s.
The performance enhancing modifications described for the 2-1-1-1 design
also apply to this design. Specifically, circuitry can be added to control CBACK
functions: first, to prevent wraparound and second, to prevent bursting when
bank described in 12,5.2 A 2-1-1-1
In fact, the PAL and address buffers are exactly the same. The PAL equations
data latches, which are now flip-flops. Also, the D-type flip-flop has been
moved from the input side of the PAL to the TERM output.
latched the "current" long word. This alteration eases access timing require-
ments such that 35-ns memory can be used with a clock frequency of 20
MHz. If the clock frequency is less than 17 MHz, 45-ns memory can be used.
16 shows four possible enable circuits.
and thus prevent or discontinue a burst cycle. The circuitry should have two
VCC
ECS -
signal is asserted within 10 ns after the rising edge of state $2. Figure 12-
-
VCC
"Q
Q
Figure 12-16. Additional Memory Enable Circuits
74F74
MC68030 USER'S MANUAL
~"
( B U F F E R E D ) - - ~ "
( B U F F E R E D ) - - ~ T
TERM
Burst Mode Memory Bank Using
TERM
m
ECS -
CLK
-
D
CLK
VCC
c
~
g
74F74
SRAMs.
12-29
1;