MC68EC040RC20A Freescale Semiconductor, MC68EC040RC20A Datasheet - Page 399

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MC68EC040RC20A

Manufacturer Part Number
MC68EC040RC20A
Description
IC MPU 32BIT 20MHZ 179-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC20A

Processor Type
M680x0 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Features
-
C.2 LOW-POWER STOP MODE
The low-power stop mode is a reduced power mode of operation, that causes the
MC68040V and MC68EC040V to remain quiescent until either a reset or non-masked
interrupt occurs. This mode of operation has four phases of operation and is triggered by
the low-power stop (LPSTOP) instruction:
MOTOROLA
1. Perform a LPSTOP broadcast cycle.
2. End integer unit (IU) instruction pipeline sequencing, which is similar to the STOP
instruction sequence (IMM data ˘ SR), at termination of the LPSTOP broadcast
cycle.
Figure C-1. MC68040V and MC68EC040V Functional Signal Groups
ATTRIBUTES
NOTE: *This signal is JS1 on the MC68EC040V.
TRANSFER
TRANSFER
TRANSFER
DATA BUS
CONTROL
ADDRESS
CONTROL
MASTER
SLAVE
BUS
Freescale Semiconductor, Inc.
For More Information On This Product,
D31–D0
A31–A0
TT0
TT1
R/W
LOCK
CIOUT
TM0
TM1
TM2
TLN0
TLN1
UPA0
UPA1
SIZ0
SIZ1
LOCKE
TS
TIP
TA
TEA
TCI
TBI
Go to: www.freescale.com
M68040 USER’S MANUAL
MC68EC040V
MC68040V
SC0
SC1
M I
BR
BG
BB
CDIS
MDIS*
RSTI
RSTO
IPEND
IPL0
IPL1
IPL2
AVEC
PST0
PST1
PST2
PST3
BCLK
SCD
LOC
LFO
V
GND
TCK
TMS
TDI
TDO
JS0
JS2
CC
BUS SNOOP CONTROL
AND RESPONSE
BUS ARBITRATION
PROCESSOR
CONTROL
INTERRUPT
CONTROL
STATUS AND
CLOCKS
TEST
POWER SUPPLY
C-3

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