MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 158

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.3.1,1 WRITE ALLOCATE.
6.3.1.2 D A T A BURST ENABLE.
6.3.1.3 CLEAR D A T A CACHE.
6.3.1.4 CLEAR ENTRY IN D A T A CACHE.
MOTOROLA
the data cache. Operating systems and other software set this bit w h e n burst
f i l l i n g of the data cache is desired. A reset operation clears the DBE bit.
mode (refer to 6,1.2.1 WRITE ALLOCATION) for w r i t e cycles. Clearing this bit
selects the n o - w r i t e - a l l o c a t i o n mode. A reset operation clears t h i s bit. The
s u p e r v i s o r s h o u l d set this bit w h e n it shares data w i t h the user task or w h e n
any task maps m u l t i p l e logical addresses to one physical address. If the data
cache is disabled or frozen, the W A bit is ignored.
f r o m the cache prior to a c o n t e x t switch. The processor clears all valid bits
to the i n d e x and l o n g - w o r d select portion of an address specifies the entry
to be cleared. The processor clears o n l y the specified long w o r d by clearing
the v a l i d bit for the entry at the t i m e a MOVEC instruction loads a one into
the CED bit of the CACR, regardless of the states of the ED and FD bits. The
data cache. Operating systems and other software set this bit to clear data
in the data cache at the t i m e a MOVEC i n s t r u c t i o n loads a one into the CD
bit of the CACR. The CD bit is a l w a y s read as a zero.
in the data cache. The index field of the CAAR (see Figure 6-15) c o r r e s p o n d i n g
CED bit is a l w a y s read as a zero.
31
000000000000000000 WA DBE CD tED FD ED 0
DBE = Data Burst Enabl e
CED = Clear Entry in Data Cache
WA = Write Allocate
IBE = Instruction Burst Enabl e
CEI = Clear Entry in Instruction Cache
CD = Clear Data Cache
ED = Enable Data Cache
FD = Freeze Data Cache
CI = Clear Instruction Cache
El = Enable Instruction Cache
FI = Freeze Instruction Cache
14 13 12 11 !0
Figure 6-14. Cache Control Register
Bit 13, the W A bit, is set to select the w r i t e - a l l o c a t i o n
MC68030 USER'S MANUAL
Bit 11, the CD bit, is set to clear all entries in the
Bit 12, the DBE bit, is set to enable burst f i l l i n g of
Bit 10, the CED bit, is set to clear an entry
9
8
7
0
6
0 IBE CI CEI FI
5
4
3
2
1
El
6-21
0
6