MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 150

• Manufacturer Part Number: MC68020FE33E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
To repair data faults (indicated by DF = 1), the software should first examine the RM bit in
the SSW to determine if the fault was generated during a read-modify-write operation. If
RM = 0, the handler should then check the RW bit of the SSW to determine if the fault was
caused by a read or a write cycle. For data write faults, the handler must transfer the
properly sized data from the data output buffer on the stack frame to the location indicated
by the data fault address in the address space defined by the SSW. (Both the data output
buffer and the data fault address are part of the stack frame at SP + $18 and SP + $10,
respectively.) Data read faults only generate the long bus fault frame, and the handler
must transfer properly sized data from the location indicated by the fault address and
address space to the image of the data input buffer at location SP + $2C of the long
format stack frame. Byte, word, and 3-byte operands are right justified in the 4-byte data
buffers. In addition, the software handler must clear the DF bit of the SSW to indicate that
the faulted bus cycle has been corrected.
To emulate a read-modify-write cycle, the exception handler must first read the operation
word at the PC address (SP + 2 of the stack frame). This word identifies the CAS, CAS2,
or TAS instruction that caused the fault. Then the handler must emulate this entire
instruction (which may consist of up to four long-word transfers) and update the CCR
portion of the SR appropriately, because the RTE instruction expects the entire operation
to have been completed if the RM bit is set and the DF bit is cleared. This is true even if
the fault occurred on the first read cycle.
To emulate the entire instruction, the handler must save the data and address registers for
the instruction (with a MOVEM instruction, for example). Next, the handler reads and
modifies (if necessary) the memory location. It clears the DF bit in the SSW of the stack
frame and modifies the condition codes in the SR copy and the copies of any data or
address registers required for the CAS and CAS2 instructions. Last, the handler restores
the registers that it saved at the beginning of the emulation. Except for the data input
buffer, the copy of the SR, and the SSW, the handler should not modify a bus fault stack
frame. The only bits in the SSW that may be modified are DF, RB, and RC; all other bits,
including those defined for internal use, must remain unchanged.
Address error faults must be repaired in software. Address error faults can be
distinguished from bus error faults by the value in the vector offset field of the format word.
6.2.3 Completing the Bus Cycles with RTE
Another method of completing a faulted bus cycle is to allow the processor to rerun the
bus cycles during execution of the RTE instruction that terminates the exception handler.
This method cannot be used to recover from address errors. The RTE instruction is
always executed. Unless the handler routine has corrected the error and cleared the fault
(and cleared the RB/RC and DF bits of the SSW), the RTE instruction cannot complete
the bus cycle(s). If the DF bit is still set at the time of the RTE execution, the faulted data
cycle is rerun by the RTE instruction. If the FB or FC bit is set and the corresponding rerun
bit (RB or RC) was not cleared by the software, the RTE reruns the associated instruction
prefetch. The fault occurs again unless the cause of the fault, such as a nonresident page
in a virtual memory system, has been corrected. If the RB or RC bit is set and the
MOTOROLA
M68020 USER’S MANUAL
6- 25
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