GCIXP1200EB Intel, GCIXP1200EB Datasheet - Page 21

• Manufacturer Part Number: GCIXP1200EB
• Description: IC NETWRK PROCESSR 200MHZ 432BGA
• Manufacturer: Intel

Specifications of GCIXP1200EB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Other names: 829764

Specification Update
This is illustrated in the following two blocks of code. The first is a test application written in C,
and the second is the test application written for the Microengine. The basic form of each is that
within a global loop, the application will:
/* Filename: tands.c */
/* test-and-set code for StrongARM* core */
/*
*/
#include <stdio.h>
#define
#define
#define CLEAR_ADDR (WORD_ADDR | 0x08000000)
#define
#define TANDS_ADDR (WORD_ADDR | 0x09800000)
#define SRAM_TEST_MOD 0x38000010
#define IXP1200_REG_READ(a,val) ((val) = *(volatile UINT32 *)(a))
#define IXP1200_REG_WRITE(a,val) (*(volatile UINT32 *)(a) = (val))
#define TANDSBIT 0x0001
#define COREBIT
int
tandsInit()
{
}
int
tandsLoop(int n)
{
4. Microengine releases semaphore:
1. Take the semaphore
2. Access locked resource
3. Release the semaphore
In word, bit 0 is used for the test and set,
Microengine clears bit 0
IXP1200_REG_WRITE(WORD_ADDR, 0);
IXP1200_REG_WRITE(DATA_ADDR, 0);
return 0;
int i=0;
int j;
int xfer;
for (; n > 0; n--) {
case 01: Another Microengine has semaphore; goto Start.
case 10: StrongARM* core has ownership, but just set bit 0, so Microengine clears bit 0
case 11: StrongARM* core has ownership, but we didn’t just set bit 0, so
while (1) {
WORD_ADDR 0x10000000
DATA_ADDR (WORD_ADDR + 4)
Loop, reading word until StrongARM* core bit (bit 1) cleared
goto Start
Loop, reading word until StrongARM* core bit (bit 1) cleared
goto Start
SET_ADDR (WORD_ADDR | 0x08800000)
bit 1 is used for StrongARM* core ownership
IXP1200_REG_WRITE(SET_ADDR, COREBIT);
IXP1200_REG_READ(WORD_ADDR, xfer);
0x0002
Intel
®
IXP1200 Network Processor
Errata
21