MC7457RX1000NC Freescale Semiconductor, MC7457RX1000NC Datasheet - Page 5

• Manufacturer Part Number: MC7457RX1000NC
• Description: IC MPU RISC 32BIT 483FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7457RX1000NC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Family Name: MPC74xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3/1.5/1.8/2.5V
• Operating Supply Voltage (max): 1.35/1.575/2.625V
• Operating Supply Voltage (min): 1.25/1.425/1.71V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 483
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
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— Space must be available in the CQ for an instruction to dispatch (this includes instructions that
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set associative instruction and data caches
— Pseudo least recently used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— L1 cache supports parity generation and checking
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
are assigned a space in the CQ but not in an issue queue)
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
words per clock cycle
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Features
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