MC8640TVU1067NE Freescale Semiconductor, MC8640TVU1067NE Datasheet - Page 86

• Manufacturer Part Number: MC8640TVU1067NE
• Description: IC MPU SGL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640TVU1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 994-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Serial RapidIO
15.9
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in clause
47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by
clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE802.3ae-2002 is specified as
the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE802.3ae-2002 is
recommended as a reference for additional information on jitter test methods.
15.9.1
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (Baud Frequency) ÷ 1667 is applied to the jitter. The data pattern for template measurements is the
continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial
link shall be active in both the transmit and receive directions, and opposite ends of the links shall use
asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane
implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The
amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10
The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V
differential. The left and right edges of the template shall be aligned with the mean zero crossing points of
the measured data eye. The load for this test shall be 100-Ω resistive ± 5% differential to 2.5 GHz.
15.9.2
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud
Frequency) ÷ 1667 is applied to the jitter. The data pattern for jitter measurements is the continuous jitter
test pattern (CJPAT) pattern defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall
be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous
clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations
shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured
with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter
tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described
in Annex 48B of IEEE802.3ae.
15.9.3
Transmit jitter is measured at the driver output when terminated into a load of 100-Ω resistive ± 5%
differential to 2.5 GHz.
15.9.4
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first
producing the sum of deterministic and random jitter defined in
and then adjusting the signal amplitude until the data eye contacts the six points of the minimum eye
opening of the receive template shown in
must have vertical waveform symmetry about the average value and have horizontal symmetry (including
jitter) about the mean zero crossing. Eye template measurement requirements are as defined above.
86
Measurement and Test Requirements
Eye Template Measurements
Jitter Test Measurements
Transmit Jitter
Jitter Tolerance
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Figure 56
and
Table
62. Note that for this to occur, the test signal
Section 15.7, “Receiver Specifications,”
Freescale Semiconductor
-12
.