MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 16

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

At recommended operating conditions with OV
Input Clocks
4
4.1
Table 6
4.2
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2 × t
no minimum RTC frequency; RTC may be grounded if not needed.
4.3
Table 7
the MPC8572E.
16
At recommended operating conditions with LV
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and 60 kHz on
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies.Refer to
settings.
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK.
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
Input Clocks
provides the system clock (SYSCLK) AC timing specifications for the MPC8572E.
provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
Parameter/Condition
System Clock Timing
Real Time Clock Timing
eTSEC Gigabit Reference Clock Timing
Parameter/Condition
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 7. EC_GTX_CLK125 AC Timing Specifications
Section 19.2, “CCB/SYSCLK PLL
Table 6. SYSCLK AC Timing Specifications
DD
DD
/TV
of 3.3V ± 5%.
DD
t
KHK
of 3.3V ± 5% or 2.5V ± 5%
Symbol
f
t
t
SYSCLK
SYSCLK
KH
/t
—
SYSCLK
, t
Symbol
KL
f
t
G125
G125
CCB
, and minimum clock low time is 2 × t
Min
7.5
0.6
33
40
—
Ratio,” and
Min
—
—
Typical
Section 19.3, “e500 Core PLL Ratio,”
Typical
1.0
—
—
—
—
125
8
+/– 150
Max
Max
30.3
133
1.2
60
—
—
Freescale Semiconductor
MHz
Unit
ns
MHz
Unit
ns
ns
ps
%
CCB
. There is
Notes
—
—
for ratio
Notes
4, 5, 6
—
1
2
3