PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet

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Features • 3000 Dhrystone 2.1 MIPS at 1.3 GHz • Selectable Bus Clock (30 CPU Bus Dividers up to 28x) • 13 Selectable Core-to-L3 Frequency Divisors • Selectable MPx/60x Interface Voltage (1.8V, 2.5V) • Selectable L3 Interface of 1.8V or ...

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... Screening • CBGA Upscreenings Based on Atmel Standards • Full Military Temperature Range (T Industrial Temperature Range (T • HCTE Package for the 7457 PC7457 2 = -55 C, +125 C -40 C, +110 suffix CBGA 483 Ceramic Ball Grid Array GH suffix HITCE 483 Ceramic Ball Grid Array 5345D–HIREL–07/06 ...

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Block Diagram Figure 1-1. PC7457 Microprocessor Block Diagram 5345D–HIREL–07/06 PC7457 3 ...

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General Parameters Table 2-1 Table 2-1. Parameter Technology Die size Transistor count Logic design Packages Core power supply I/O power supply 3. Overview This section summarizes features of the PC7457 implementation of the PowerPC architecture. Major features of the ...

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Four integer units (IUs) that share 32 GPRs for integer operands – Five-stage FPU and a 32-entry FPR file – Four vector units and 32-entry vector register file (VRs) – Three-stage load/store unit (LSU) 5345D–HIREL–07/06 Eight-entry link register stack ...

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Dedicated adder calculates effective addresses (EAs) Supports store gathering Performs alignment, normalization, and precision conversion for floating-point data Executes cache control and TLB instructions Performs alignment, zero padding, and sign extension for integer data Supports hits under misses (multiple outstanding ...

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Instruction cache can provide four instructions per clock cycle; data cache can – Caches can be disabled in software – Caches can be locked in software – MESI data cache coherency maintained in hardware – Separate copy of data ...

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Memory programmable as write-back/write-through, caching-inhibited/caching- allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis – Separate IBATs and DBATs (eight each) also defined as SPRs – Separate instruction and data translation lookaside buffers (TLBs) ...

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Thermal management facility provides software-controllable thermal management. – Instruction cache throttling provides control of instruction fetching to limit power • Performance monitor can be used to help debug system designs and improve software efficiency • In-system testability and debugging ...

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Signal Description Figure 4-1. PC7457 Microprocessor Signal Groups Address Arbitration A[0:35] Address AP[0:4] Transfer TT[0:4] TBST Address TSIZ[0:2] Transfer GBL Attributes AACK ARTRY Address Transfer SHD0/SHD1 Termination DBG Data DTI[0:3] Arbitration DRDY D[0:63] Data DP[0:7] Transfer Data Transfer Termination ...

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... Detailed Specification This specification describes the specific requirements for the microprocessor PC7457 in compli- ance with Atmel standard screening. 6. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein. ...

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Recommended Operating Conditions Symbol Characteristic V Core supply voltage DD (2) AV PLL supply voltage Processor bus supply voltage bus supply voltage DD ( Input ...

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Table 6-1. BVSEL Signal 0 ¬HRESET HRESET 1 Notes: 6.2 Thermal Characteristics 6.2.1 Package Characteristics Table 6-2. Package Thermal Characteristics Symbol Characteristic (2)(3) R Junction-to-ambient thermal resistance, natural convection JA (2)(4) R Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board ...

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Package Thermal Characteristics for HCTE Table 6-3 Table 6-3. Characteristic Junction-to-bottom of balls Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction to board thermal resistance Notes: 6.2.3 Internal Package Conduction Resistance For the exposed-die packaging technology, shown in ...

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Thermal Management Information This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design – the heat sink, airflow, and thermal interface ...

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Figure 6-4. 6.2.5.1 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows where the die-junction temperature the inlet cabinet ambient ...

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For this example ature below the maximum value of Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a com- mon figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise ...

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Figure 6-5. Recommended Thermal Model of PC7447 and PC7457 Conductivity Bump and Underfill Substrate k Solder Ball and Air 6.2.6 Power Consumption Table 6-4. Full-Power Mode Core Power ...

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Electrical Characteristics 7.1 Static Characteristics Table 7-1 provides the DC electrical characteristics for the PC7457 Table 7-1. DC Electrical Specifications (see Symbol Characteristic ( Input high voltage (all inputs including SYSCLK (2)(6) V ...

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Dynamic Characteristics This section provides the AC electrical characteristics for the PC7457. After fabrication, func- tional parts are sorted by maximum processor core frequency as shown in section “Clock AC Specifications” and tested for conformance to the AC specifications ...

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Symbol Characteristic t / KHKL SYSCLK duty cycle measured at OV (4) t SYSCLK (5)(6) SYSCLK jitter Internal PLL relock time Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre- ...

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Processor Bus AC Specifications Table 7-3 ure 7-10 on page 33 provided in section Table 7-3. Processor Bus AC Timing Specifications (2) Symbol Parameter Input setup times: t A[0:35], AP[0:4] AVKH t D[0:63], DP[0:7] DVKH t AACK, ARTRY, BG, ...

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The symbology used for timing specifications herein follows the pattern for outputs. For example, t (reference)(state)(signal)(state) the SYSCLK reference (K) going to the high (H) state or input setup time. And t going high (H) until ...

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Figure 7-3 Figure 7-3. Input/Output Timing Diagram SYSCLK All Inputs All Outputs (Except TS, ARTRY, SHD0, SHD1) t KHOE All Outputs (Except TS, ARTRY, SHD0, SHD1) TS ARTRY, SHD0, SHD1 Note: 7.2.3 L3 Clock AC Specifications The L3_CLK frequency is ...

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Note that SYSCLK input jitter and L3_CLK[0:1] output jitter are already comprehended in the L3 bus AC timing specifications and do not need to be separately accounted for timing analysis. Clock skews, where applicable, do need ...

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Figure 7-4. L3_CLK_OUT Output Timing Diagram L3_CLK0 L3_CLK1 For PB2 or Late Write: L3_ECHO_CLK1 L3_ECHO_CLK3 7.2.4 L3 Bus AC Specifications The PC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate (DDR) MSUG2 SRAM, Late Write SRAMs, ...

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More specifically, certain signals within groups should be delay-matched with others in the same group while intergroup routing is less critical. Only the address and control signals are common to both SRAMs and additional timing margin is available for these ...

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Table 7-6. Effect of L3OHCR Settings on L3 Bus AC Timing (1) Field name Affected Signals L3_ADDR[18:0], L3AOH L3_CNTL[0:1] All signals latched by SRAM L3CLKn_OH connected to L3_CLKn L3_DATA[n:n + 7], L3DOHn L3_DP[n/8] Notes: 1. Refer to the PC7450 RISC ...

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An internal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal receiving latches. This delayed clock is used to capture the data into these latches which comprise the receive FIFO. ...

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Assumes default value of L3OHCR. See information I/O voltage mode must be configured by L3VSEL as described in must match mode selected as specified in Figure 7-6 shows the typical connection diagram for the PC7457 interfaced to ...

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Inputs L3_ECHO_CLK[0,1,2,3] L3 Data and Data Parity Inputs Notes and t as drawn here will be negative numbers, that is, input setup time will be time after the clock edge. L3DVEH L3DVEL Midpoint Voltage (GV ...

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Figure 7-8 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs. Figure 7-8. Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface PC7457 Denotes Receive (SRAM to PC7457) Aligned Signals Denotes ...

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Figure 7-9 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs. Figure 7-9. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs Outputs L3_CLK[0,1] L3_ECHO_CLK[1,3] t L3CHOV ADDR, L3_CNTL t L3CHDV L3DATA ...

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Table 7-9. JTAG AC Timing Specifications (Independent of SYSCLK) (see “Recommended Operating Conditions Symbol Parameter Input Setup Times: (3) t Boundary-scan data DVJH t TMS, TDI IVJH Input Hold Times: (3) t Boundary-scan data DXJH t TMS, TDI IXJH Valid ...

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Figure 7-13. TRST Timing Diagram Note: Figure 7-14. Boundary-scan Timing Diagram Note: Figure 7-15. Test Access Port Timing Diagram Note: 5345D–HIREL–07/06 VM TRST VM = Midpoint Voltage (OV /2) DD TCK VM Boundary Data Inputs t JLDV t JLDX Boundary ...

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Preparation for Delivery 8.1 Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, ...

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Figure 8- Figure 8-2. 5345D–HIREL–07/06 Pinout of the PC7457, 483 CBGA and HCTE Package as Viewed from the Top Surface ...

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Table 8-1. Pinout Listing for the PC7457, 483 CBGA and HCTE Packages Signal Name Pin Number E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2, N2, P8, M8, W4, (2) A[0:35] N6, U6, R5, Y4, P1, P4, ...

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Table 8-1. Pinout Listing for the PC7457, 483 CBGA and HCTE Packages (Continued) Signal Name Pin Number INT J6 (10) L1_TSTCLK H4 (12) L2_TSTCLK J2 (6)(7) L3VSEL A4 H11, F20, J16, E22, H18, G20, F22, G22, H20, K16, J18, H22, ...

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Table 8-1. Pinout Listing for the PC7457, 483 CBGA and HCTE Packages (Continued) Signal Name Pin Number (13) TEST[0:5] B10, H6, H10, D8, F9, F8 (10) TEST[6] A9 (7) TMS K4 (7)(16) TRST C1 ( TSIZ[0:2] L1,H3,D1 TT[0:4] ...

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Mechanical Dimensions for the PC7457, 483 CBGA Figure 9-1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 CBGA package. Figure 9-1. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457, 483 CBGA Package A1 CORNER ...

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Substrate Capacitors for the PC7457, 483 CBGA Figure 10-1 shows the connectivity of the substrate capacitor pads for the PC7457, 483 CBGA. All capacitors are 100 nF. Figure 10-1. Substrate Bypass Capacitors for the PC7457, 483 CBGA A1 CORNER ...

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Mechanical Dimensions for the PC7457, 483 HCTE Figure 11-1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 HCTE package. Figure 11-1. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457, 483 HCTE Package A1 CORNER ...

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Substrate Capacitors for the PC7457, 483 HCTE Figure 12-1 shows the connectivity of the substrate capacitor pads for the PC7457, 483 HCTE. All capacitors are 100 nF. Figure 12-1. Substrate Bypass Capacitors for the PC7457, 483 HCTE A1 CORNER ...

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Mechanical Dimensions for the PC7457, 483 HCTE ROHS compliant Figure 13-1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 HCTE package. Figure 13-1. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457, 483 HCTE Package ...

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Figure 14-1. Substrate Bypass Capacitors for the PC7457, 483 HCTE A1 CORNER C1-1 C2-1 C1-2 C2-2 C18-2 C17-2 C16-2 C18-1 C17-1 PC7457 46 C3-1 C4-1 C5-1 C6-1 C3-2 C4-2 C5-2 C6-2 C15-2 C14-2 C13-2 C16-1 C15-1 C14-1 C13-1 Pad Number ...

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System Design Information This section provides system and thermal design recommendations for successful application of the PC7457. 15.1 Clocks The following sections provide more detailed information regarding the clocking o fthe PC7457. 15.1.1 Core Clocks and PLL Configuration The ...

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Table 15-1. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (Continued) Bus-to-Core Core-to-VCO PLL_CFG[0:4] Multiplier 10101 10x 10001 10.5x 10011 11x 00000 11.5x 10111 12x 11111 12.5x 01011 13x 11100 13.5x 11001 14x 00011 15x 11011 16x 00001 17x ...

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In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the ...

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System Bus Clock (SYSCLK) and Spread Spectrum Sources Spread spectrum clock sources are an increasingly popular way to control electromagnetic inter- ference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude ...

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Decoupling Recommendations Due to the PC7457 dynamic power management feature, large address and data buses, and high operating frequencies, the PC7457 can generate transient power surges and high fre- quency noise in its power supply, especially while driving large ...

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Figure 15-2. Driver Impedance Measurement Table 15-4 temperature and is relatively unaffected by bus voltage. Table 15-4. 15.6 Pull-up/Pull-down Resistor Requirements The PC7457 requires high-resistive (weak: 4 pull-up resistors on several control pins of the bus interface to ...

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During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the PC7457 must continually monitor these signals ...

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The COP header shown in and memory examination/modification, and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has ...

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Figure 15-3. JTAG Interface Connection From Target Board Sources (if any KEY 13 No Pin 15 16 COP Connector Physical Pin Out Notes: 1. RUN/STOP, normally found ...

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... For availability of the different versions, contact your local Atmel sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by Atmel. Reliability of a PCX part-number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes ...

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... Date Substantive Change(s) D 03/06 Remove PC7447. Modification Updated document to new Atmel template Updated section numbering and changed reference from part number specifications to addendums Added Rev. 1.2 devices, including increased L3 clock max frequency to 250 MHz and improved L3 AC timing Table 6-2 on page Table 7-2 on page specification to cycle-to-cycle jitter (instead of long- and short-term jitter) ...

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Table of Contents Features .................................................................................................... 1 Description ............................................................................................... 1 Screening .................................................................................................. 2 1 Block Diagram .......................................................................................... 3 2 General Parameters ................................................................................. 4 3 Overview ................................................................................................... 4 4 Signal Description ................................................................................. 10 5 Detailed Specification ............................................................................ 11 6 Applicable Documents .......................................................................... ...

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Definitions .............................................................................................. 56 17 Ordering Information ............................................................................. 56 18 Document Revision History .................................................................. 57 Table of Contents ...................................................................................... i PC7457 ii 15.6 Pull-up/Pull-down Resistor Requirements ...........................................................52 15.7 JTAG Configuration Signals ................................................................................53 16.1 Life Support Applications .....................................................................................56 5345D–HIREL–07/06 ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...