PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 30

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 7-6
Figure 7-6.
Note:
Figure 7-7
Figure 7-7.
Note:
30
8. Assumes default value of L3OHCR. See
9. L3 I/O voltage mode must be configured by L3VSEL as described in
1. Or as recommended by SRAM manufacturer for single-ended clocking.
t
(PC7457 to SRAM)
L3CHDV
Receive (SRAM
PC7457
Aligned Signals
Aligned Signals
shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs.
shows the L3 bus timing diagrams for the PC7457 interfaced to MSUG2 SRAMs.
information.
must match mode selected as specified in
to PC7457)
Outputs
Denotes
Transmit
Denotes
PC7457
L3DATA WRITE
ADDR, L3CNTL
Typical Source Synchronous 4M bytes L3 Cache DDR Interface
L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
and t
L3_CLK[0,1]
L3CLDV
as drawn here will be negative numbers, that is, output valid time will be time before the clock edge.
VM
{L3DATA[16:31], L3DP[2:3]}
t L3CHOV
{L3DATA[0:15], L3DP[0:1]}
{L3DATA[32:47], L3DP[4:5]}
{L3DATA[48:63], L3DP[6:7]}
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
“Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27
L3ECHO_CLK[2]
L3ADDR[18:0]
L3_CNTL[0]
L3_CNTL[1]
“Recommended Operating Conditions
L3_CLK[0]
t L3CHDV
L3_CLK[1]
t L3CHDX
VM
t L3CHOX
t L3CHOZ
Table 6-1 on page
VM
t L3CLDV
(1)
” on page
t L3CLDX
t L3CLDZ
SA[18:0]
B1
B2
CQ
D[0:17]
CK
D[18:35]
CQ
SA[18:0]
B1
B2
CQ
D[0:17]
CK
D[18:35]
CQ
VM
13, and voltage supplied at G
SRAM 0
SRAM 1
12.
LBO
LBO
CQ
CQ
CQ
CQ
CK
CK
B3
B3
G
G
VM
GND
GND
GND
NC
NC
GND
GND
GND
NC
NC
GV DD /2
GV DD /2
5345D–HIREL–07/06
for more
(1)
(1)
V
DD