PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 40

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 8-1.
Notes:
40
Signal Name
TEST[0:5]
TEST[6]
TMS
TRST
TS
TSIZ[0:2]
TT[0:4]
WT
V
VDD_SENSE[0:1]
DD
(3)
(3)
(7)
(7)(16)
1. OV
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 k ) to maintain the control signals in the negated state after they
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
5. This signal must be negated during reset, by pull up to OV
6. See
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode.
10. These input signals for factory use only and must be pulled down to GND for normal machine operation.
11. Power must be supplied to GV
12. It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect
13. These input signals are for factory use only and must be pulled up to OV
14. These signals are for factory use only and must be left unconnected for normal machine operation.
15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17. These pins are internally connected to V
(10)
PC7457
(13)
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1])
and the L3 control signals L3_CNTL[0:1]; and V
become AV
page
have been actively negated and released by the PC7457 and other bus masters.
high.
proper operation.
performance.
present at the processor core. If unused, they must be connected directly to V
DD
Pinout Listing for the PC7457, 483 CBGA and HCTE Packages (Continued)
Table 6-1 on page 13
12.
supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GV
(17)
DD
Pin Number
B10, H6, H10, D8, F9, F8
A9
K4
C1
P5
L1,H3,D1
F1, F4, K8, A5, E1
L2
J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15, M10, M12,
M14, N9, N11, N13, N15, P10, P12, P14
G11, J8
). For actual recommended value of V
.
for bus voltage configuration information. If used, pull-down resistors should be less than 250 .
DD
, even when the L3 interface is disabled or unused.
DD
. They are intended to allow an external device to detect the core voltage level
DD
supplies power to the processor core and the PLL (after filtering to
IN
or supply voltages, see
DD
or negation by ¬HRESET (inverse of HRESET), to ensure
DD
for normal machine operation.
“Recommended Operating Conditions
DD
or left unconnected.
Active
High
High
High
Low
Low
Low
–
–
–
–
Output
Output
Input
Input
Input
Input
I/O
I/O
I/O
–
–
5345D–HIREL–07/06
I/F Select
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
N/A
N/A
(1)
” on
DD
(1)