Z8018006PEC Zilog, Z8018006PEC Datasheet - Page 78

• Manufacturer Part Number: Z8018006PEC
• Description: IC 6MHZ Z180 CMOS ENH MPU 64-DIP
• Manufacturer: Zilog

Specifications of Z8018006PEC

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3005

MMU Common/Bank Area Register (CBAR)
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
Operation Mode Control Register
PS014004-1106
Bit
Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3
R/W
Mnemonic CBAR
Address 3A
CBAR
areas: Common Area, Bank Area and Common
Area 1.
CA3–CA0:CA (bits 7-4)—
(on 4 KB boundaries) for the Common Area 1, and also determines the most recent address
of the Bank Area. All bits of CA are set to
BA–BA0 (bits 3-0)—
Bank Area, and also determines the most recent address of the Common Area 0. All bits of
BA
Mnemonic OMCR
Address 3E
The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and
the Hitachi 64180. The Operating Mode
7
are set to
specifies boundaries within the Z80180 64-KB logical address space for up to three
R/W
CA2
6
1
during
R/W
CA1
5
RESET
BA
specifies the start (Low) address (on 4-KB boundaries) for the
CA0
R/W
4
.
CA
specifies the start (Low) address
R/W
BA3
3
1
during
R/W
BA2
2
RESET
R/W
BA1
1
.
R/W
BA0
0
Microprocessor Unit
Architecture
Z80180
72