Z8018110FEC Zilog, Z8018110FEC Datasheet - Page 42

• Manufacturer Part Number: Z8018110FEC
• Description: IC 10MHZ ACCESS CTRL 100-QFP
• Manufacturer: Zilog

Specifications of Z8018110FEC

• Processor Type: Z180
• Features: Smart Access Controller SAC™
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Zilog
PIA Control Registers
PIA1 Data Direction Register (P1DDR, I/O Address E0h),
PIA1 Data Port (P1DP, I/O address E1h), PIA2 Data Direc-
tion Register (P2DDR, I/O Address E2h) and PIA2 Data
Register (P2DP, I/O Address E3h). These four registers are
The Data Port is the register to/from the 8-bit parallel port.
At power on Reset, they are initialized to 1.
The Data Direction Register has eight control bits. Individ-
ual bits specify each bit's direction. When the bit is set to
2-42
Figure 51. PIA 1 Data Direction Register
E0H
E1H
7
7
6
Figure 52. PIA 1 Data Register
6
5
5
4
4
3
3
2
2
1
1
0
0
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
PIA 1
I/O Data
PS009701-0301
shown in Figures 51-54. Note that if the CTC/PIA bit in the
System Configuration Register is set to one, the CTC I/O
functions override the PIA1 function, and programming of
P1DDR is ignored.
a "1", the bit becomes an input, otherwise it is an output. On
reset, these registers are initialized to 1, resulting in all lines
being inputs.
E2H
Figure 53. PIA 2 Data Direction Register
7
E3H
7
6
Figure 54. PIA 2 Data Register
6
5
5
4
4
3
3
2
2
1
1
S
0
MART
0
A
CCESS
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
PIA 2
I/O Data
C
DS971800500
ONTROLLER
Z80181
SAC
™