TG80960JT100 Intel, TG80960JT100 Datasheet

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TG80960JT100

Manufacturer Part Number

TG80960JT100

Description

IC MPU I960JT 3V 100MHZ 132-QFP

Manufacturer

Intel

Datasheet

1.TG80960JT100.pdf (86 pages)

Specifications of TG80960JT100

Rohs Status

RoHS non-compliant

Processor Type

i960

Features

JT suffix, 32-Bit, 16k Cache, Extended Temp

Speed

100MHz

Voltage

3V

Mounting Type

Surface Mount

Package / Case

132-QFP

Other names

824389

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

TG80960JT100

Manufacturer:

PHI

Quantity:

74 910

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

TG80960JT100

Manufacturer:

Intel

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Meier Automation Equipment Co., Limited

Part Number:

TG80960JT100

Manufacturer:

INTEL

Quantity:

20 000

Current page: 1 of 86
Download datasheet (5Mb)

80960JA/JF/JD/JS/JC/JT 3.3 V

Embedded 32-Bit Microprocessor

Product Features

Code Compatible with all 80960Jx

Processors

High-Performance Embedded Architecture

Two-Way Set Associative Instruction

Cache

Direct Mapped Data Cache

On-Chip Stack Frame Cache

— One Instruction/Clock Execution

— Core Clock Rate is:

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

— 80960JA - 2 Kbyte

— 80960JF/JD - 4 Kbyte

— 80960JS/JC/JT - 16 Kbyte

— Programmable Cache-Locking

— 80960JA - 1 Kbyte

— 80960JF/JD - 2 Kbyte

— 80960JS/JC/JT - 4 Kbyte

— Write Through Operation

— Seven Register Sets May Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

1x the Bus Clock for 80960JA/JF/JS

2x the Bus Clock for 80960JD/JC

3x the Bus Clock for 80960JT

Mechanism

Interrupts

On-Chip Data RAM

3.3 V Supply Voltage

High Bandwidth Burst Bus

High-Speed Interrupt Controller

Two On-Chip Timers

Halt Mode for Low Power

IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

Packages

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

— 5 V Tolerant Inputs

— TTL Compatible Outputs

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

— 31 Programmable Priorities

— Eight Maskable Pins plus NMI#

— Up to 240 Vectors in Expanded Mode

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— Internal Interrupt Sources

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack

— 196-Ball Mini Plastic Ball Grid Array

(PQFP)

(MPBGA)

Order Number: 273159-006

Datasheet

August 2004

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