MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 140

• Manufacturer Part Number: MC68360RC25K
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360RC25K

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bus Operation
NOTES:
1.The reset behavior is this case is dependent on the PLL programming (see 6.9.3.9 CLKO Control Register (CLKOCR)).
2.Doesn't cause a CPU32 reset exception nor does it affect any of its internal registers.
If an external device drives RESETS or RESETH low, they should be asserted for at least
32 clock periods to ensure that the QUICC resets. When the reset control logic detects that
an external device drives RESETS low, it starts driving both internal and external RESETS
low for 512 cycles to guarantee this length of reset to the entire system. When the reset con-
trol logic detects that an external device drives RESETH low, it starts driving both internal
and external RESETS and RESETH low for 512 cycles to guarantee this length of reset to
the entire system. The external and the internal resets are released after the external device
stops driving the external reset signal low or after the 512 cycles, whatever is later. Figure
4-46 shows the reset timing.
If reset is asserted from any other source, the reset control logic asserts a reset for a mini-
mum of 512 cycles and until the source of reset is negated.
After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence
of an external reset. If no external reset is detected, the CPU32+ begins its vector fetch.
Figure 4-47 is a timing diagram of the power-up reset operation, showing the relationships
between RESETH, RESETS, VCC, and bus signals. During the reset period, the entire bus
three-states (except for non-three-statable signals, which are driven to their inactive state).
4-64
External Hard Reset (RESETH)
External Soft Reset (RESETS)
Power-Up
Software Watchdog
Double Bus Fault
Loss of Clock
Reset Instruction
1
RESETS OR
Type
RESETH
RESETS signal will always be negated after 512 cycles after as-
sertion.
Figure 4-46. Timing for External Devices Driving RESET
Freescale Semiconductor, Inc.
PULLED EXTERNAL
Table 4-9. Reset Source Summary
For More Information On This Product,
T
Sys Prot
Sys Prot
CPU32+
External
External
Source
Clock
EBI
32 CLKS
MC68360 USER’S MANUAL
Go to: www.freescale.com
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
512 CYCLES
Timing
NOTE
INTRST
INTRST
INTRST
INTRST
INTRST
INTRST
INTRST
Reset Lines Asserted by Controller
2
INTSYSRST
INTSYSRST
INTSYSRST
INTSYSRST
INTSYSRST
T 14 CLKS
—
—
CLKRST
CLKRST
CLKRST
CLKRST
—
—
—
EXTSYSRST
EXTSYSRST
EXTSYSRST
EXTSYSRST
EXTSYSRST
EXTRST
EXTRST