MPC852TVR50 Freescale Semiconductor, MPC852TVR50 Datasheet - Page 20

• Manufacturer Part Number: MPC852TVR50
• Description: IC MPU POWERQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TVR50

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bus Signal Timing
1
2
3
4
5
6
7
8
9
10
20
Num
B39
B40
B41
B42
B43
in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum
allowed jitter on EXTAL can be up to 2%.
BG input is relevant when the MPC852T is selected to work with external bus arbiter.
asserted.
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
and B38 are specified to enable the freeze of the UPM output signals as described in
in
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values
For part speeds above 50MHz, use 9.80ns for B11a.
The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for
For part speeds above 50MHz, use 2ns for B17.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
For part speeds above 50MHz, use 2ns for B19.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
Figure
AS valid to CLKOUT rising edge
x B1 + 7.00)
A(0:31), TSIZ(0:1), RD/WR, BURST, valid to
CLKOUT rising edge (MIN = 0.00 x B1 + 7.00)
TS valid to CLKOUT rising edge (setup time)
(MIN = 0.00 x B1 + 7.00)
CLKOUT rising edge to TS valid (hold time)
(MIN = 0.00 x B1 + 2.00)
AS negation to memory controller signals
negation (MAX = TBD)
21.
Characteristic
Table 9. Bus Operation Timings (continued)
MPC852T Hardware Specifications, Rev. 3.1
10
(MIN = 0.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
7.00
7.00
7.00
2.00
Min
—
40 MHz
Max
TBD
—
—
—
—
Figure
7.00
7.00
7.00
2.00
Min
—
50 MHz
18.
Max
TBD
—
—
—
—
Freescale Semiconductor
7.00
7.00
7.00
2.00
Min
—
66 MHz
Max
TBD
—
—
—
—
Unit
ns
ns
ns
ns
ns