QU80386EXTC33 Intel, QU80386EXTC33 Datasheet - Page 14

• Manufacturer Part Number: QU80386EXTC33
• Description: IC INT PROC 5V 33MHZ 132QFP
• Manufacturer: Intel

Specifications of QU80386EXTC33

• Processor Type: 386EX
• Features: 32-bit, Extended Temp
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863827

Intel386™ EX Embedded Microprocessor
14
Table 4.
Intel386™ EX Microprocessor Pin Descriptions (Sheet 2 of 6)
D15:0
DACK1:0#
D/C#
DCD1:0
DRQ1:0
DSR1:0#
DTR1:0#
EOP#
ERROR#
FLT#
HLDA
HOLD
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Symbol
Type
I/OD
I/O
O
O
O
O
I
I
I
I
I
I
Output States
R(WH)
R(WH)
R(WL)
H(Z)
R(Z)
P(X)
H(Z)
H(X)
P(X)
H(Z)
P(X)
P(Z)
H(1)
R(1)
R(1)
P(0)
P(Z)
H(1)
I(Q)
I(Q)
I(0)
I(X)
I(Z)
Data Bus inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during memory
and I/O write cycles. During writes, this bus is driven during
phase 2 of T1 and remains active until phase 2 of the next T1,
T1P, or Ti. During reads, data is latched on the falling edge of
phase 2.
DMA Acknowledge 1 and 0 signal to an external device that the
processor has acknowledged the corresponding DMA request
and is relinquishing the bus. DACK1# is multiplexed with TXD1,
and DACK0# is multiplexed with CS5#.
Data/Control indicates whether the current bus cycle is a data
cycle (memory or I/O read or write) or a control cycle (interrupt
acknowledge, halt, or code fetch).
Data Carrier Detect SIO1 and SIO0 indicate that the modem or
data set has detected the corresponding asynchronous serial
channel’s data carrier. DCD1# is multiplexed with DRQ0, and
DCD0# is multiplexed with P1.0 and has a temporary weak pull-
up resistor.
DMA External Request 1 and 0 indicate that a peripheral
requires DMA service. DRQ1 is multiplexed with RXD1, and
DRQ0 is multiplexed with DCD1#.
Data Set Ready SIO1 and SIO0 indicate that the modem or data
set is ready to establish a communication link with the
corresponding asynchronous serial channel. DSR1# is
multiplexed with STXCLK and has a permanent weak pull-up
resistor, and DSR0# is multiplexed with P1.3 and has a
temporary weak pull-up resistor.
Data Terminal Ready SIO1 and SIO0 indicate that the
corresponding asynchronous serial channel is ready to establish
a communication link with the modem or data set. DTR1# is
multiplexed with SRXCLK, and DTR0# is multiplexed with P1.2.
End of Process indicates that the processor has reached
terminal count during a DMA transfer. An external device can
also pull this pin LOW. EOP# is multiplexed with CTS1#.
Error indicates that the math coprocessor has an error condition.
ERROR# is multiplexed with TMROUT2 and has a temporary
weak pull-up resistor.
Float forces all bidirectional and output signals except TDO to a
high-impedance state. It has a permanent weak pull-up resistor.
This pin should be tied to V
resistor.
Bus Hold Acknowledge indicates that the processor has
surrendered control of its local bus to another bus master. HLDA
is multiplexed with P1.7.
Bus Hold Request allows another bus master to request control
of the local bus. HLDA active indicates that bus control has been
granted. HOLD is multiplexed with P1.6. It has a temporary weak
pull-down resistor.
Name and Function
CC
through a 3 to 7 KOhm pull-up
Datasheet