MC68882EI33A Freescale Semiconductor, MC68882EI33A Datasheet - Page 11

• Manufacturer Part Number: MC68882EI33A
• Description: IC FLOAT-PT COPROC 33MHZ 68PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68882EI33A

• Processor Type: Floating-Point Co-Processor
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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~~~~~~the precepts
MC-
BRW/Rev.
think of the MC68882 as though
fications;<~J~@~entation
with the MC68882 than the MC68881, The offsets for the
exceptional
are 32 bytes more than that of the MC68881. However,
unique
bling the system software
MISCELLANEOUS
the status, control, and instruction
state of the MC68882.
Thus, if the MC68882 instructs the MC68020 or MC68030
to transfer
cubations
instruction
ent only on the value of the command
the MC68882 by the main processor.
of the MC68020 and MC68030. Some addressing
are restricted
erand).
flexible
or MC68030.
by the coprocessor
metic is coded exactly like inta$erjarithmetic.
not require&@~~*are
structi@W
per~~’@&e
g~.,~mtee
~~stems-level
grade
ated by the FSAVE instruction)
BIU flag word from the top of the saved idle state frame
included
FRESTORE instructions
FMOVE
FMOVE
FSAVE
FRESTORE
MC68020 or MC68030 performs
MC68030, and the execution
mode to be used with floating-point
M68000
mediate,
register direct, and the indexedfindirect
Family
relative
MC68030
The MC68882 does not perform
This interface
The orthogonal
Using the ~~~,~~~~n
First, note that the idle and busy state frames
.. .
Miscellaneous
the system to operate properly
format
architectural
branches and addressing
addressing
Family,
postincrement,
are the virtual
~~~cution
requested
allow
3
that the floating-point
,,
an operand
<ea>, FPcr
FPcr,<ea>
<es>
<es>
is encoded
operand,
advantage
for instructions
There are no specia~ ‘~~t~$cllons
MC6W8PQ6MPATIBILITY
.,.
software
word
ADDRESSING
,, ~ :,:-: ..,“+
a programmer
instructions
is flexible
.>$:,.d~”
these
instruction
of a sequential
INSTRUCTIONS
is not allowed
concurrency
in the instruction,
is generated
definitions
interface, ~~’~;~$j~ating-point
the operand
.~,\p\+
,~t. ,’.,.1, . ‘.-,
changes
via the coprocessor
that save and restore the internal
\.$~ , , ‘ :*1** ,i.$l+
specifically
an existing
modifications
addressing
over the MC68881. However,
predecrement,
Move to Control Register(s)
Move from Control Register(s)
Virtual Machine State Save
Virtual Machine State Restore
memory/machine
!::,’ ~.~
.:,:,
,,,, :s.,:,. i d.:,~,\.
of multiple
to detect this difference.
-> .,
and allows
consistent
set of the MC6~$&~$the
of the MC68882 is depend-
‘~ *,*.,
include moves to and from
Freescale Semiconductor, Inc.
,,”
the addressing
nor user-software
are both 32 bytes larger
MODES
it is,,~~$~fithe
or a cQ~p~&’’writer
For More Information On This Product,
(e.g.; program
modes o&~~~~r68020/
exception
execution
address registers, Also
gives
register word, and the
by the MC68882 ens-
address calculations,
MC68881 socket does
for a destination
for the MC68020
instructions,
modes
with an MC68882.
are needed to up-
addressing
floating-point
with the M6800&$Y;~$,:j
In this case, the
word written
the MC68882
any addressing
data or address
Go to: www.freescale.com
interface,
model, some
model main-
... . .
include
FSAVE and
mode cal-
:~:.,.,
MC68020
imposed
. . ,,, ,,..
,7{!’*:,
counter
(gener-
For the
modes
modes
~s?
modi-
.
arith-
The
o~~
the
im-
in-
to
or
to
to
a
a
“’ik,
.. .. . ,,.
~k;%k:,,f~
rY’~fi@ groups
floating-point
tions. For interrupt
~~~~~,coprocessor.
ADDRESS BUS (AO through A4)
from being restored
handlers
structions,
implemented.
ofj~e
main processor
ister locations
lines control
unique format
(Signaling
(Overflow),
imum
+
The above requirements
The$~.UoWtng
These active-high
Second, the BSUN (Branch or Set on Unordered),
The terms assetiion
sively to avoid confusion
assertion
or true, independent
or negation
active or false.
low” and “active-high”
resented
.. ..... . . .,,
3. An FRESTORE instruction
1. An FSAVE must
2, A BSET or sjmilar
iti~,ut and output signals for the MC68882 floating-
requirements:
the BI U flag word (located in the sa~~~J~T& state
frame),
fore the RTE instruction.
floating-point
,!s’.!..?,~,$ 1’
RESET
SENSE
Figure 10. MC68882 Input/Output
“Cc
GNO
m
CLK
FMN~~@~
that do not conta~d~ny’%oating-point
j;
Not-A-Number),
DZ (Divide by Zero) and INEX (Inexact result)
by a high or low voltage. The term negate
as shown in Figure 10.
only
is used to indicate
the register
~,:i ,1,$,, ‘~$+:$
~,c
,>.
exception
located
.,
>
word prevents
/
*
is used to indicate
P
>
.. .. . ...... . .... . >. . ,..,,.. .............. . ..... .,. . ”...,., ,,,..,.,,, . ,..., . . . .,.................;,..,.,,,
to select the coprocessor
paragraphs
*;!$*N ,,.~:$?
13
..<
req~?~gmnts
7
The signals are functionally
~$’&,\
hand~~~~wt
FLOATING-POINT
~~t,~ *<>,*,
address line inputs
into an MC68882 and vice versa.
COPROCESSOR
\.$\.h . .
SIGNAL DESCRIPTIONS
instruction,
,.
,.3M , :,. *
~.+ ,..,,
in the CPU address space. These
MC6B882
and negation
of whether
handlers
be executed
NOTE
selection ‘as listed in Table 3.
instruction
signals. The term assert or
OPERR (Operand Error), OVFL
are ~&J<~p]icable
when describing
contain
a saved MC68881 context
that a signal
,.,
,t>.?:.~~$
have floating-point
mus$~~i>kecuted
#1 and #3
must have these min-
that a signal
~~,,o +t’:s
.. .
\\ *1,>
‘.<.! .. . .:.~!
that level is rep-
4
4
*
*
a brief description
are used exten-
that sets’~~%1
before
,,,
are used by the
Signals
DSACKO
<. ‘ Stk, itl?,)$,,
DO-D31
DSACK1
‘.. ::>.. ~ .(i:,$.’
interface
AO-A4
fl~
m
E
E
,., .
to interrupt
is active
MOTOROLA
,,
“active-
any other
organized
..
must
is in-
instruc-
.. ~ ~~.j$
,,-
SNAN
*
*
reg-
1
be-
in-
be
11
of
,.
.;,