XPC850SRVR50BU Freescale Semiconductor, XPC850SRVR50BU Datasheet - Page 10

• Manufacturer Part Number: XPC850SRVR50BU
• Description: IC MPU POWERQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of XPC850SRVR50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Signal Timing
θ
P
P
P
For most applications P
relationship between P
P
Solving equations (1) and (2) for K gives:
K = P
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P
solving equations (1) and (2) iteratively for any value of T
5.1
Each V
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip V
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V
planes.
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data busses. Maximum PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
Special care should be taken to minimize the noise levels on the PLL supply pins.
6
Table 6
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF. Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
10
JA
D
INT
I/O
D
D
= P
= K ÷ (T
(at equilibrium) for a known T
= Package thermal resistance
= Power dissipation on input and output pins—user determined
= I
D
INT
DD
CC
Bus Signal Timing
•
provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
(T
+ P
Layout Practices
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each
x V
A
J
I/O
+ 273°C)(2)
+ 273°C) + θ
DD
,
CC
watts—chip internal power
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
D
I/O
and T
< 0.3
JA
• P
J
is:
D
•
,
2
junction to ambient
A
P
(3)
. Using this value of K
INT
and can be neglected. If P
CC
power supply should be bypassed to ground using at least four
,
°C/W
CC
,
A
the values of P
.
and GND should be kept to less than half an
I/O
is neglected
D
and T
,
an approximate
J
can be obtained by
Freescale Semiconductor
CC
and GND