LUPXA255A0C300 Intel, LUPXA255A0C300 Datasheet - Page 10

• Manufacturer Part Number: LUPXA255A0C300
• Description: IC MICRO PROCESSOR 300MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C300

• Processor Type: XScale®
• Speed: 300MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866869

Summary of Changes
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Status
No Fix
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Summary of Errata (Sheet 1 of 2)
“MAC Instructions May Not Be Executed During Debug Mode”
“Jtag Highz Instruction Not 1149.1 Compliant”
“Instruction Fetch Unit (IFU) Misses an External Abort”
“MultiMediaCard Stream Data Writes Do Not Transmit Properly”
“Watchdog Reset Causes The Real Time Clock (RTC) To Increment
At The Wrong Frequency”
“Drain Write Buffer Command Does Not Force All Memory Requests
Out To The External Bus”
“Unindexed Mode LDC/STC Instructions Can Corrupt Protected
Registers”
“Aborted Store That Hits the Data Cache Marks Write-back Data
Dirty”
“A Load That Follows a DTLB Invalidate Entry Command Will Also
Be Invalidated.”
“SDRAM Auto Power Down Does Not Shut Off SDCLKs 0, 1, and 2
When Their Respective Partitions Are Not Being Accessed”
“Memory Controller GPIO Pins Float High After Reset and Cause a
Write to Address 0x0”
“The SPI Protocol In The MMC Is Giving CRC Errors On Every
Commands Response.”
“MMC Compatibility issue with different brand MMC cards.”
“MMC SPI mode – if card is deselected, PROG_DONE will not be
set.”
“AC97 Transmits invalid data on the PXA255 processor with 66Mhz
Core/33Mhz Memclk.”
“Long idle time on external bus between DREQ and nCS for flow-
through DMA.”
“MMC - invalid data can be written to card if user stops then restarts
the clock prior to end of data transfer.”
“PMU monitoring event #1, cycles in which the I-cache cannot
deliver an instruction, is incorrectly incremented”
“In Special Debug State, back to back memory transactions may
hang if the first memory operation receives a precise data abort.”
“The first access to a disabled SDRAM partition will not do a refresh
cycle.”
“Error occurs if memory access starts within last 32 bytes of a 64MB
region of static/PCMCIA memory.”
“Overrun on the Receive FIFO for the PCM channel of the AC97 unit
will leave the FIFOs in an unrecoverable state.”
“SET_FEATURE/CLEAR_FEATURE Request with an illegal feature
selector value will cause the UDC controller to respond incorrectly.”
“The JTAG Controller must have the 3.6864 MHz oscillator running
to work.”
Intel® PXA255 Processor Specification Update
ERRATA