MC7448VS1700LC Freescale Semiconductor, MC7448VS1700LC Datasheet - Page 3

• Manufacturer Part Number: MC7448VS1700LC
• Description: IC MPU RISC 1700MHZ 360-FCCLGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VS1700LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCLGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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This section summarizes features of the MPC7448 implementation.
Major features of the MPC7448 are as follows:
Freescale Semiconductor
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Features
High-performance, superscalar microprocessor
— Up to four instructions can be fetched from the instruction cache at a time.
— Up to three instructions plus a branch instruction can be dispatched to the issue queues at a
— Up to 12 instructions can be in the instruction queue (IQ).
— Up to 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
— Four integer units (IUs) that share 32 GPRs for integer operands
— Five-stage FPU and 32-entry FPR file
time.
– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
– IU2 executes miscellaneous instructions, including the CR logical operations, integer
– Fully IEEE Std. 754™-1985–compliant FPU for both single- and double-precision
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
the first four instructions in the target stream.
prediction—not taken, strongly not taken, taken, and strongly taken
often removed from the instruction stream.
Register (bclr) instructions
multiply, divide, and move to/from special-purpose register instructions.
multiplication and division instructions, and move to/from special-purpose register
instructions.
operations
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Features
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