LTC4266CGW#PBF Linear Technology, LTC4266CGW#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC4266CGW#PBF
• Description: IC CTRLR IEEE 802.3AT 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC4266CGW#PBF

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Input Voltage: 3.3V
• Supply Current: -2.4mA
• Digital Ic Case Style: SSOP
• No. Of Pins: 36
• Duty Cycle (%): 60%
• Uvlo: 25V
• Frequency: 1MHz
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 36
• Mounting: Surface Mount
• Package Type: SSOP
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

APPLICATIONS INFORMATION
The LTC4266 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
t
MOSFET Fault Detection
LTC4266 PSE ports are designed to tolerate significant
levels of abuse, but in extreme cases it is possible for
the external MOSFET to be damaged. A failed MOSFET
may short source to drain, which will make the port ap-
pear to be on when it should be off; this condition may
also cause the sense resistor to fuse open, turning off
the port but causing the LTC4266 SENSE pin to rise to
an abnormally high voltage. A failed MOSFET may also
short from gate to drain, causing the LTC4266 GATE pin
to rise to an abnormally high voltage. The LTC4266 SENSE
and GATE pins are designed to tolerate up to 80V faults
without damage.
If the LTC4266 sees any of these conditions for more than
180μs, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again. The remaining ports of
the LTC4266 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a t
to turn on the port.
Voltage and Current Readback
The LTC4266 measures the output voltage and current
at each port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
• Slow mode: 14 samples per second, 14.5 bits resolution
• Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte are
zeroes so that bit scaling is the same in both modes.
LIM
setting.
START
fault if the LTC4266 attempts
Disconnect
The LTC4266 monitors the port to make sure that the PD
continues to draw the minimum specified current. A dis-
connect timer counts up whenever port current is below
7.5mA (typ), indicating that the PD has been disconnected.
If the t
the disconnect bit in the fault event register will be set.
If the current returns before the t
timer resets and will start counting from the beginning
if the undercurrent condition returns. As long as the PD
exceeds the minimum current level more often than t
it will stay powered.
Although not recommended, the DC disconnect feature can
be disabled by clearing the corresponding DC Disconnect
Enable bits. Note that this defeats the protection mecha-
nisms built into the IEEE spec, since a powered port will
stay powered after the PD is removed. If the still-powered
port is subsequently connected to a non-PoE data device,
the device may be damaged.
The LTC4266 does not include AC disconnect circuitry, but
includes AC disconnect enable bits to maintain compat-
ibility with the LTC4259A. If the AC Disconnect Enable bits
are set, DC disconnect will be used.
Shutdown Pins
The LTC4266 includes a hardware SHDN pin for each port.
When a SHDN pin is pulled to DGND, the corresponding
port will be shut off immediately. The port remains shut
down until re-enabled via I
pin mode.
Masked Shutdown
The LTC4266 provides a low latency port shedding fea-
ture to quickly reduce the system load when required. By
allowing a pre-determined set of ports to be turned off,
the current on an overloaded main power supply can be
reduced rapidly while keeping high priority devices pow-
ered. Each port can be configured to high or low priority;
all low-priority ports will shut down within 6.5μs after
the MSD pin is pulled low. If multiple ports in a LTC4266
device are shut down via MSD, they are staggered by at
least 0.55μs to help reduce voltage transients on the main
DIS
timer expires, the port will be turned off and
2
C or a device reset in AUTO
DIS
timer runs out, the
LTC4266
21
4266fb
DIS
,