SJA1000T/N1,112 NXP Semiconductors, SJA1000T/N1,112 Datasheet - Page 17

• Manufacturer Part Number: SJA1000T/N1,112
• Description: IC STAND-ALONE CAN CTRLR 28-SOIC
• Manufacturer: NXP Semiconductors

Specifications of SJA1000T/N1,112

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: CAN
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 15 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3994-5; 935230920112; SJA1000TD; SJA1000TD

Philips Semiconductors
6.3.6
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the
INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating
level at INT. The interrupt register appears to the microcontroller as a read only memory.
Table 6 Bit interpretation of the interrupt register (IR); CAN address 3
Notes
1. Reading this bit will always reflect a logic 1.
2. A wake-up interrupt is also generated if the CPU tries to set go to sleep while the CAN controller is involved in bus
3. The overrun interrupt bit (if enabled) and the data overrun status bit are set at the same time.
4. The receive interrupt bit (if enabled) and the receive buffer status bit are set at the same time.
2000 Jan 04
IR.7
IR.6
IR.5
IR.4
IR.3
IR.2
IR.1
IR.0
Stand-alone CAN controller
activities or a CAN interrupt is pending.
It should be noted that the receive interrupt bit is cleared upon a read access, even if there is another message
available within the FIFO. The moment the release receive buffer command is given and there is another message
valid within the receive buffer, the receive interrupt is set again (if enabled) with the next t
BIT
I
NTERRUPT
WUI
DOI
EI
TI
RI
SYMBOL
R
EGISTER
Wake-Up Interrupt;
note 2
Data Overrun Interrupt;
note 3
Error Interrupt
Transmit Interrupt
Receive Interrupt; note 4 1
(IR)
NAME
1
0
1
0
1
0
1
0
0
VALUE
17
reserved; note 1
reserved; note 1
reserved; note 1
set; this bit is set when the sleep mode is left
reset; this bit is cleared by any read access of the
microcontroller
set; this bit is set on a ‘0-to-1’ transition of the data
overrun status bit, when the data overrun interrupt
enable is set to logic 1 (enabled)
reset; this bit is cleared by any read access of the
microcontroller
set; this bit is set on a change of either the error
status or bus status bits if the error interrupt
enable is set to logic 1 (enabled)
reset; this bit is cleared by any read access of the
microcontroller
set; this bit is set whenever the transmit buffer
status changes from logic 0 to logic 1 (released)
and transmit interrupt enable is set to logic 1
(enabled)
reset; this bit is cleared by any read access of the
microcontroller
set; this bit is set while the receive FIFO is not
empty and the receive interrupt enable bit is set
to logic 1 (enabled)
reset; this bit is cleared by any read access of the
microcontroller
FUNCTION
scl
.
Product specification
SJA1000