CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 46

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HSS Transmit Gap Register [0xC074] [R/W]
Register Description
The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted
thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equivalent to two
stop bits.
Transmit Gap Select (Bits [7:0])
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *
bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.
Reserved
All reserved bits must be written as ‘0’.
HSS Data Register [0xC076] [R/W]
Register Description
The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data.
The Transmit Ready Flag in the HSS Control register must read ‘1’ before writing to this register (this avoids disrupting the
previous/current transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits must be written as ‘0’.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
15
15
X
X
0
7
0
7
-
-
R/W
R/W
14
14
X
6
X
0
6
0
-
-
Figure 50. HSS Transmit Gap Register
R/W
R/W
Figure 51. HSS Data Register
13
13
X
X
5
0
5
0
-
-
R/W
Transmit Gap Select
R/W
12
12
X
0
X
4
4
0
-
-
Reserved
Reserved
Data
R/W
R/W
11
11
X
0
X
3
3
1
-
-
R/W
R/W
10
10
X
X
0
2
2
0
-
-
R/W
R/W
X
1
X
9
0
9
-
1
0
-
CY7C67200
Page 46 of 78
R/W
R/W
X
X
0
8
0
8
-
-
0
1
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