Z16C3220FSG Zilog, Z16C3220FSG Datasheet - Page 113

• Manufacturer Part Number: Z16C3220FSG
• Description: IC 20MHZ CMOS IUSC 80-QFP
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3220FSG

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC CHARACTERISTICS
Timing Table
113
Z
ILOG
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
Tcyc
TwASl
TwASh
TwDSl
TwDSh
TdAS(DS)
TdDS(AS)
TdDS(DRa)
TdDS(DRv)
TdDS(DRn)
TdDS(DRz)
TsCS(AS)
ThCS(AS)
TsADD(AS)
ThADD(AS)
TsSIA(AS)
ThSIA(AS)
TsAD(AS)
ThAD(AS)
TsRW(DS)
ThRW(DS)
TsDSf(RRQ)
TdDSr(RRQ)
TsDW(DS)
ThDW(DS)
TdDSf(TRQ)
TdDSr(TRQ)
TwRDl
TwRDh
TdAS(RD)
TdRD(AS)
TdRD(DRa)
TdRD(DRv)
TdRD(DRn)
TdRD(DRz)
TdRDf(RRQ)
TdRDr(RRQ)
TwWRl
TwWRh
TdAS(WR)
TdWR(AS)
TsDW(WR)
ThDW(WR)
TdWRf(TRQ)
Bus Cycle Time
/AS Low Width
/DS Low Width
/AS Rise to /DS Fall Delay Time
/DS Rise to /AS Fall Delay Time
Parameter
/AS High Width
/DS High Width
/DS Fall to Data Active Delay
/DS Fall to Data Valid Delay
/DS Rise to Data Not Valid Delay
/DS Rise to Data Float Delay
/CS to /AS Rise Setup Time
/CS to /AS Rise Hold Time
Direct Address to /AS Rise Setup Time
Direct Address to /AS Rise Hold Time
Status /INTACK to /AS Rise Setup Time
Status /INTACK to /AS Rise Hold Time
Address to /AS Rise Setup Time
Address to /AS Rise Hold Time
R//W to /DS Fall Setup Time
R//W to /DS Fall Hold Time
/DS Fall to /RxREQ Inactive Delay
/DS Rise to /RxREQ Active Delay
Write Data to /DS Rise Setup Time
Write Data to DS Rise Hold Time
/DS Fall to /TxREQ Inactive Delay
/DS Rise to /TxREQ Active Delay
/RD Low Width
/RD High Width
/AS Rise to /RD Fall Delay Time
/RD Rise to /AS Fall Delay Time
/RD Fall to Data Active Delay
/RD Fall to Data Valid Delay
/RD Rise to Data Not Valid Delay
/RD Rise to Data Float Delay
/RD Fall to /RxREQ Inactive Delay
/RD Rise to /RxREQ Active Delay
/WR Low Width
/WR High Width
/AS Rise to /WR Fall Delay Time
/WR Rise to /AS Fall Delay Time
Write Data to /WR Rise Setup Time
Write Data to /WR Rise Hold Time
/WR Fall to /TxREQ Inactive Delay
P R E L I M I N A R Y
Min
160
40
90
70
60
15
15
15
15
25
30
70
60
70
60
30
5
5
0
0
5
5
5
5
0
0
0
0
5
5
0
0
0
5
5
0
Max
85
20
60
60
85
20
60
60
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PS97USC0200
Z16C32 IUSC
Note
[1]
[1]
[4]
[5]
[4]
[5]
™