Z8023010VSC Zilog, Z8023010VSC Datasheet - Page 19

• Manufacturer Part Number: Z8023010VSC
• Description: IC 10MHZ Z8000 CMOS ESCC 44-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z8023010VSC

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS005308-0609
When the receiver is enabled, the CPU is interrupted in one of the following three meth-
ods:
1. Interrupt on First Receive Character or Special Receive Condition
2. Interrupt on All Receive Characters or Special Receive Conditions
3. Interrupt on Special Receive Conditions Only
If WR7’ bit 3 is 1, and the Special Receive Condition is selected, the Receive character
occurs when there are four bytes available in the Receive FIFO. This is most useful in syn-
chronous applications as the data is in consecutive bytes. Interrupt on First Character or
Special Condition and Interrupt on Special Condition Only are typically used with the
BLOCK TRANSFER mode. A special Receive Condition consists of one of the follow-
ing:
•
•
•
•
The Special Receive Condition interrupt is different from an ordinary receive character
available interrupt only by the status placed in the vector during the Interrupt Acknowl-
edge cycle. In Receive Interrupt on First Character or Special Condition mode, an inter-
rupt occurs from Special Receive Conditions any time after the first receive character
interrupt.
The primary function of the External/Status interrupt is to monitor the signal transitions of
the CTS
any of the following:
•
•
•
•
•
The interrupt caused by the ABORT or EOP sequence has a special feature that allows the
ESCC to interrupt when the ABORT or EOP sequence is detected or terminated. This fea-
ture facilitates the proper termination of the current message, correct initialization of the
next message, and the accurate timing of the ABORT condition by external logic in SDLC
mode. SDLC LOOP mode allows secondary stations to recognize the primary station and
regain control of the loop during a poll sequence.
Receiver Overrun
Framing error in ASYNCHRONOUS mode
EOF in SDLC mode
Parity error (optional)
A Transmit Underrun condition
A zero count in the BRG
A detection of a Break (ASYNCHRONOUS mode)
An ABORT (SDLC mode)
An End Of Poll (EOP) sequence in the data stream (SDLC LOOP mode)
,
DCD, and SYNC pins. However, an External/Status interrupt is also caused by
Product Specification
Functional Description
Z80230/Z85230/L
14