ISP1161ABM ST-Ericsson Inc, ISP1161ABM Datasheet - Page 51

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ISP1161ABM

Manufacturer Part Number
ISP1161ABM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161ABM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3150

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ST-Ericsson Inc
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Philips Semiconductors
Table 16:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Table 17:
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 03 — 23 December 2004
Description
MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
reserved
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
0 — ignore
1 — enable interrupt generation due to Frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
0 — ignore
1 — enable interrupt generation due to Resume Detect
0 — ignore
1 — enable interrupt generation due to Start of Frame
reserved
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
Full-speed USB single-chip host and device controller
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
reserved
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reserved
ISP1161A
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
50 of 134
SO
24
16
0
0
8
0
0
0

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