ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 22

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
8.6.3 DC interrupt output pin (INT2)
To re-enable the interrupt generation:
Remark: Bit InterruptPinEnable in the HcHardwareConfiguration register latches the
interrupt output. When this bit is set to logic 0, the interrupt output will remain
unchanged, regardless of any operations on the interrupt control registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal
without clearing the HcµPInterrupt register, the following procedure should be
followed:
To re-enable the interrupt generation:
The four configuration modes of DC’s interrupt output pin INT2 can also be
programmed by setting bits INTPOL and INTLVL of the DcHardwareConfiguration
register (BBH - read, BAH - write). Bit INTENA of the DcMode register (B9H - read,
B8H - write) is used to enable pin INT2.
interrupt events and pin INT2.
Each of the indicated USB events is logged in a status bit of the DcInterrupt register.
Corresponding bits in the Interrupt Enable register determine whether or not an event
will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the DcMode
register (see
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the DcHardwareConfiguration register (see
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the
DcInterrupt register. The endpoint bits (EP0OUT to EP14) are cleared by reading the
associated DcEndpointStatus register.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the DcInterrupt register.
SETUP and OUT token interrupts are generated after the DC has acknowledged the
associated data packet. In bulk transfer mode, the DC will issue interrupts for every
ACK received for an OUT token or transmitted for an IN token.
1. Set all bits in the HcµPInterrupt register.
2. Set bit InterruptPinEnable to logic 1.
1. Make sure that bit InterruptPinEnable is set to logic 1.
2. Clear all bits in the HcµPInterruptEnable register.
3. Set bit InterruptPinEnable to logic 0.
1. Set all bits in the HcµPInterruptEnable register according to the HCD
2. Set bit InterruptPinEnable to logic 1.
requirements.
Table
Rev. 03 — 23 December 2004
81).
Full-speed USB single-chip host and device controller
Figure 21
shows the relationship between the
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
ISP1161A
83). Default
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