ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 80

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 66:
[1]
[2]
9397 750 13962
Product data
Endpoint
identifier
0
0
1 to 14
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
IN: input for the USB host (ISP1161A transmits); OUT: output from the USB host (ISP1161A receives). The data flow direction is
determined by bit EPDIR in the DcEndpointConfiguration register; see
Endpoint access and programmability
FIFO size (bytes)
64 (fixed)
64 (fixed)
programmable
11.3.1 Endpoints with programmable FIFO size
11.3.2 Endpoint access
11.3.3 Endpoint FIFO size
11.3 Endpoint descriptions
A DMA transfer is terminated when any of the following conditions are met:
When the DMA transfer is terminated, the buffer is also cleared (even if the data is not
completely read) and the DMA handler is disabled automatically. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
device. At design time each endpoint is assigned a unique number (endpoint
identifier, see
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The DC has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either via
the Programmed I/O interface or via DMA.
Table 66
I/O mode access. Endpoints 1 to 14 also support DMA access. DC FIFO DMA
access is selected and enabled via bits EPIDX[3:0] and DMAEN of the
DcDMAConfiguration register. A detailed description of the DC DMA operation is
given in
The size of the FIFO determines the maximum packet size that the hardware can
support for a given endpoint. Only enabled endpoints are allocated space in the
shared FIFO storage, disabled endpoints have zero bytes.
programmable FIFO sizes.
The following bits in the DcEndpointConfiguration register (ECR) affect FIFO
allocation:
•
•
•
The DMA count is complete
DMAEN = 0
The DMA controller asserts EOT.
[1]
Section
lists the endpoint access modes and programmability. All endpoints support
Double
buffering
no
no
supported
Table
Rev. 03 — 23 December 2004
12.
66). The combination of the device address (given by the host
Full-speed USB single-chip host and device controller
I/O mode
access
yes
yes
supported
Section 13.1.1
DMA mode
access
no
no
supported
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 67
Endpoint type
control OUT
control IN
programmable
ISP1161A
lists the
[2]
[2]
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