STE10/100A STMicroelectronics, STE10/100A Datasheet - Page 34

• Manufacturer Part Number: STE10/100A
• Description: IC CTRLR PCI ETHERNET 128-PQFP
• Manufacturer: STMicroelectronics

Specifications of STE10/100A

• Controller Type: Ethernet Controller, 10Base-T
• Interface: PCI
• Voltage - Supply: 3.14 V ~ 3.46 V
• Current - Supply: 130mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3663

Registers and descriptors description
34/82
Table 6.
CR3 (offset = 0ch), LT - Latency timer
CR4 (offset = 10h), IOBA - I/O base address
CR5 (offset = 14h), MBA - Memory base address
CR11 (offset = 2ch), SID - Subsystem ID
CR12 (offset = 30h), BRBA - Boot ROM base address. This register should be initialized before
accessing the boot ROM space.
31~16
31~16
15~ 8
31~ 7
31~ 7
15~ 0
7 ~ 0
6 ~ 1
6 ~ 1
Bit #
0
0
Configuration registers description (continued)
Name
IOBA
SVID
MBA
CLS
IOSI
IOSI
SID
LT
---
---
---
Reserved
Latency timer. This value specifies the latency timer
of the STE10/100A in units of PCI bus clock cycles.
Once the STE10/100A asserts FRAME#, the latency
timer starts to count. If the latency timer expires and
the STE10/100A is still asserting FRAME#, the
STE10/100A will terminate the data transaction as
soon as its GNT# is removed.
Cache line size. This value specifies the system
cache line size in units of 32-bit double words (DW).
The STE10/100A supports cache line sizes of 8, 16,
or 32 DW. CLS is used by the STE10/100A driver to
program the cache alignment bits (bit 14 and 15 of
CSR0) which are used for cache oriented PCI
commands, for example, memory-read-line,
memory-read-multiple, and memory-write-and-
invalidate.
I/O base address. This value indicate the base
address of PCI control and status register
(CSR0~28), and transceiver registers (XR0~10).
Reserved
I/O space indicator.
1: means that the configuration registers map into
I/O space.
Memory base address. This value indicate the base
address of PCI control and status
register(CSR0~28), and transceiver
registers(XR0~10).
Reserved
Memory space indicator.
1: means that the configuration registers map into
I/O space.
Subsystem ID. This value is loaded from EEPROM
as a result of power-on or hardware reset.
Subsystem vendor ID. This value is loaded from
EEPROM as a result power-on or hardware reset.
Description
EEPROM
EEPROM
Default
From
From
40h
08h
0
1
0
0
STE10/100A
RW type
R/W
R/W
R/W
R/W
RO
RO
RO
RO