DP8409AN National Semiconductor, DP8409AN Datasheet - Page 14

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

DP8409A Functional Mode Descriptions
Note that RASIN going low earlier than t
low may result in the DP8409A interpreting the RASIN as a
hidden refresh RASIN if no hidden refresh has occurred in
the current RFCK cycle In this case all RAS outputs would
go low for a short time Thus it is suggested that when
using Mode 5 RASIN should be held high until t
CS goes low if a refresh is not intended Similarly CS should
be held low for a minimum of t
when ending the access in Mode 5
MODE 6 FAST AUTOMATIC ACCESS
The Fast Access mode is similar to Mode 5 but has a faster
t
fast 16k or 64k DRAMs (which have a t
15 ns) in applications requiring fast access times RASIN to
CAS is typically 105 ns
In this mode the R C (RFCK) pin is not used but CASIN
(RGCK) is used as CASIN to allow an extended CAS after
RAS has already terminated Refer to Figure 8b This is de-
RAH
of 20 ns minimum It therefore can only be used with
(Strobed by ADS)
B1
0
0
1
1
Bank Select
TABLE II Memory Bank Decode
FIGURE 10 Change in Propagation Delay vs Loading Capacitance Relative to a 500 pF Load
B0
0
1
0
1
CSRL
after RASIN returns high
Enabled RAS
CSRL
RAH
RAS
RAS
RAS
RAS
after CS goes
0
1
2
3
of 10 ns to
CSRL
n
after
14
(Continued)
sirable with fast cycle-times where RAS has to be terminat-
ed as soon as possible before the next RAS begins (to meet
the precharge time or t
CAS may then be held low by CASIN to extend the data
output valid time from the DRAM to allow the system to read
the data CASIN subsequently going high ends CAS If this
extended CAS is not required CASIN should be set high in
Mode 6
There is no internal refresh-request flip-flop in this mode so
any refreshing required must be done by entering Mode 0 or
Mode 2
MODE 7 SET END-OF-COUNT
The End-of-Count can be externally selected in Mode 7
using ADS to strobe in the respective value of B1 and B0
(see Table III) With B1 and B0 the same EOC is 127 with
B1
until the next Mode 7 selection At power-up the EOC is
automatically set to 127 (B1 and B0 set to 11)
e
0 EOC is 511 This selected value of EOC will be used
e
0 and B0
B1
(Strobed by ADS)
0
0
1
1
Bank Select
e
1 EOC is 255 and with B1
TABLE III Mode 7
TL F 8409 – 20
B0
0
1
0
1
RP
requirements of the DRAM)
End of Count
Selected
127
255
511
127
e
1 and B0