DP83256VF National Semiconductor, DP83256VF Datasheet - Page 10

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

3 0 Functional Description
Framing may be temporarily suspended (i e framing hold)
in order to maintain data integrity
Detecting JK
The JK symbol pair can be used to detect the beginning of a
frame during Active Line State (ALS) and Idle Line State
(ILS) conditions
While the Line State Detector indicates Idle Line State the
receiver ‘‘reframes’’ upon detecting a JK symbol pair and
enters the Active Line State
During Active Line State acceptance of a JK symbol (re-
framing) is allowed for any on-boundary JK which is detect-
ed at least 1 5 byte times after the previous JK
During Active Line State once reframed on a JK a subse-
quent off-boundary JK is ignored even if it is detected be-
yond 1 5 byte times after the previous JK
During Active Line State an Idle or Ending Delimiter (T)
symbol will allow reframing on any subsequent JK if a JK is
detected at least 1 5 byte times after the previous JK
Detecting HALT-HALT AND HALT-QUIET
During Idle Line State the detection of a Halt-Halt or Halt-
Quiet symbol pair will still allow the reframing of any subse-
quent on-boundary JK
Once a JK is detected during Active Line State off-bounda-
ry Halt-Halt or Halt-Quiet symbol pairs are ignored until the
Elasticity Buffer (EB) has an opportunity to recenter They
are treated as violations
After recentering on a Halt-Halt or Halt-Quiet symbol pair
all off boundary Halt-Halt or Halt-Quiet symbol pairs are ig-
nored until the EB has a chance to recenter during a line
state other than Active Line State (which may be as long as
2 8 byte times)
SYMBOL DECODER
The Symbol Decoder is a two level system The first level is
a 5-bit to 4-bit converter and the second level is a 4-bit
symbol pair to byte-wide code converter
The first level latches the received 5-bit symbols and de-
codes them into 4-bit symbols Symbols are decoded into
two types data and control The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder See Table 3-1 for the 5B 4B Symbol Decoding
list
The second level translates two symbols from the 5B 4B
converter and the line state information from the Line State
Detector into the National byte-wide code
LINE STATE DETECTOR
The ANSI X3T9 5 FDDI Physical Layer (PHY) standard
specifies eight Line States that the Physical Layer can
transmit These Line States are used in the Connection
Management process They are also used to indicate data
within a frame during normal operation
The Line States are reported through the Current Receive
State Register (CRSR) Receive Condition Register A
(RCRA) and Receive Condition Register B (RCRB)
(Continued)
10
Note V denotes PHY Invalid or an Elasticity Buffer stuff byte
I denotes Idle symbol in ILS or an Elasticity Buffer stuff byte
LINE STATES DESCRIPTION
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair)
The Line State Detector continues to indicate Active Line
State while receiving data symbols Ending Delimiter (T
symbols) and Frame Status symbols (R and S) after the JK
symbol pair
Idle Line State
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases)
Idle Line State indicates the preamble of a frame or the lack
of frame transmission during normal operation Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process
I (Idle)
H (Halt)
JK (Starting
T (Ending
R (Reset)
S (Set)
Q (Quiet)
V (Violation)
V
V
V
V
V
V
V
Symbol
Delimiter)
Delimiter)
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
TABLE 3-1 5B 4B Symbol Decoding
Incoming 5B
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
00100
11000 and
10001
01101
00111
11001
00000
00001
00010
00011
00101
00110
01000
01100
10000
Decoded 4B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1010
0001
1101
0101
0110
0111
0010
0010
0010
0010
0010
0010
0010
0010
0010